User's Manual

S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER
21-15
START
Set Block Size Reg
(1)
Set Block Count Reg
(2)
Set Argument Reg
(3)
Set Transfer Mode Reg
(4)
Set Command Reg
(5)
Set System Address Reg
(6)
Wait for Command
Complete Int
Clr Command Complete
Status
Command Complete Int occur
Get Response Data
(7)
(8)
(9)
Wait for Transfer
Complete Int and DMA Int
Check Interrupt Status
DMA Int occur
Transfer Complete Int
occur
Clr DMA Status Interrupt
Set System Address Reg
(10)
(11)
(12)
(13)
Clr Transfer Complete status
Clr DMA Interrupt status
(14)
END
Figure 21-12. Transaction Control with Data Transfer Using DAT Line Sequence (Using DMA)
(1) Set the system address for DMA in the System Address register.
(2) Set the value corresponding to the executed data byte length of one block in the Block Size register.
(3) Set the value corresponding to the executed data block count in the Block Count register(BLKCNT).
(4) Set the value corresponding to the issued command in the Argument register(ARGUMENT).
(5) Set the values for Multi / Single Block Select and Block Count Enable.
And at this time, set the value corresponding to the issued command for Data Transfer Direction, Auto CMD12
Enable and DMA Enable.
(6) Set the value corresponding to the issued command in the Command register(CMDREG).
NOTE: When writing to the upper byte of the Command register, the SD command is issued and DMA is started.
(7) And then wait for the Command Complete Interrupt.
(8) Write 1 to the Command Complete(STACMDCMPLT) in the Normal Interrupt Status register to clear this bit.
(9) Read Response register and get necessary information in accordance with the issued command.