User's Manual

HS_SPI CONTROLLER S3C2450X RISC MICROPROCESSOR
20-10
Register Address R/W Description Reset Value
HS_SPI_STATUS(Ch0
)
0x52000014 R HS_SPI status register 0x0
HS_SPI_STATUS(Ch1
)
0x59000014 R HS_SPI status register 0x0
HS_SPI_STATUS Bit Description Initial State
TX_done [21]
Indication of transfer done in Shift register
0 = all case except blow case
1 = when tx fifo and shift register are empty
* Master mode only
1’b0
Trailing_count_done [20]
Indication that trailing count is zero
1’b0
RxFifoLvl [19:13]
Data level in RX FIFO
0 ~ 7’h40 byte
7’b0
TxFifoLvl [12:6]
Data level in TX FIFO
0 ~ 7’h40 byte
7’b0
RxOverrun [5]
Rx Fifo overrun error
0 = No error
1 = Overrun error
1’b0
RxUnderrun [4]
Rx Fifo underrun error
0 = No error
1 = Underrun error
1’b0
TxOverrun [3]
Tx Fifo overrun error
0 = No error
1 = Overrun error
1’b0
TxUnderrun [2]
Tx Fifo underrun error
0 = No error
1 = Underrun error
* If TX fifo empty, always occur at slave mode
1’b0
RxFifoRdy [1]
0 = Data in FIFO less than trigger level
1 = Data in FIFO more than trigger level
1’b0
TxFifoRdy [0]
0 = Data in FIFO more than trigger level
1 = Data in FIFO less than trigger level
1’b0