User's Manual

HS_SPI CONTROLLER S3C2450X RISC MICROPROCESSOR
20-8
Register Address R/W Description Reset Value
MODE_CFG(Ch0) 0x52000008 R/W HS_SPI FIFO control register 0x0
MODE_CFG(Ch1) 0x59000008 R/W HS_SPI FIFO control register 0x0
MODE_CFG Bit Description Initial State
Ch_tran_size [30:29] 00 = Byte
01 = Halfword
10 = Word
11 = Reserved
2’b0
Trailing Count [28:19] Count value from writing the last data in RX FIFO to flush
trailing bytes in FIFO
10’b0
BUS transfer size [18:17]
00 = Byte
01 = Halfword
10 = Word
11 = Reserved
2’b0
RxTrigger [16:11] Rx FIFO trigger level in INT mode.
Trigger level is from 0 to 63. The value means byte number in
RX FIFO
6’b0
TxTrigger [10:5] Tx FIFO trigger level in INT mode
Trigger level is from 0 to 63. The value means byte number in
TX FIFO
6’b0
reserved [4:3]
− −
RxDMA On [2] DMA mode on/off
0 = DMA mode off
1 = DMA mode on
1’b0
TxDMA On [1] DMA mode on/off
0 = DMA mode off
1 = DMA mode on
1’b0
DMA transfer [0] DMA transfer type, single or 4 bust.
0 = Single
1 = 4 burst
DMA transfer size should be set as the same size in DMA as it
in HS_SPI.
1’b0
** Channel Transfer size must be smaller than Bus Transfer size or the same as.