User's Manual

2D S3C2450X RISC MICROPROCESSOR
19-36
Stencil Test
5.3.42 Colorkey Control Register (COLORKEY_CTRL_REG)
Register Address R/W Description Reset Value
COLORKEY_CTRL
_REG
0x4D408720 R/W Colorkey Control Register 0x0
Field Bit Description Initial State
Reserved [31:5]
−
0x0
StencilInverse [4] 0 = Normal stencil test
1 = Inversed stencil test
This bit should be set to 0 if the stencil test of every color field is
disabled.
0x0
StencilOnR [3] 0 = Stencil Test Off for R value
1 = Stencil Test On for R value
0x0
StencilOnG [2] 0 = Stencil Test Off for G value
1 = Stencil Test On for G value
0x0
StencilOnB [1] 0 = Stencil Test Off for B value
1 = Stencil Test On for B value
0x0
StencilOnA [0] 0 = Stencil Test Off for A value
1 = Stencil Test On for A value
0x0
5.3.43 Colorkey Decision Reference Minimum Register (COLORKEY_DR_MIN_REG)
Register Address R/W Description Reset Value
COLORKEY_DR_
MIN_REG
0x4D408724 R/W Colorkey Decision Reference Minimum Register 0x0
Field Bit Description Initial State
A_DR(min) [31:24] Alpha DR MIN value 0x0
R_DR(min) [23:16] RED DR MIN value 0x0
G_DR(min) [15:8] GREEN DR MIN value 0x0
B_DR(min) [7:0] BLUE DR MIN value 0x0