User's Manual

2D S3C2450X RISC MICROPROCESSOR
19-20
5.2.4 Host to Screen Continue BitBLT Register (CMD3_REG)
Register Address R/W Description Reset Value
CMD3_REG 0x4D40810C W Host to Screen Continue BitBLT Register 0x0
Field Bit Description Initial State
Data [31:0] BitBLT data (Continue)
Note that the data written to this register represents only one pixel,
regardless of the source color mode. If the source color mode is
16-bpp (e.g., RGB565), the upper 16 bits of the data are ignored.
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5.2.5 Host to Screen Start Color Expansion Register (CMD4_REG)
Register Address R/W Description Reset Value
CMD4_REG 0x4D408110 W Host to Screen Start Color Expansion Register 0x0
Field Bit Description Initial State
Data [31:0] Color Expansion Data (Start)
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5.2.6 Host to Screen Continue Color Expansion Register (CMD5_REG)
Register Address R/W Description Reset Value
CMD5_REG 0x4D408114 W Host to Screen Continue Color Expansion Register 0x0
Field Bit Description Initial State
Data [31:0] Color Expansion Data (Continue)
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5.2.7 Memory to Screen Color Expansion Register (CMD7_REG)
Register Address R/W Description Reset Value
CMD7_REG 0x4D40811C W Memory to Screen Color Expansion Register 0x0
Field Bit Description Initial State
Memory
Address
[31:0] Bitmap data base address (used in memory-to-screen mode,
should be word-aligned).
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