User's Manual

S3C2450X RISC MICROPROCESSOR 2D
19-17
5.1.3 FIFO Interrupt Control Register (FIFO_INTC_REG)
Register Address R/W Description Reset Value
FIFO_INTC_REG 0x4D408008 R/W FIFO Interrupt Control 0x18
Field Bit Description Initial State
Reserved [31:6]
−
0x0
FIFO_INT_LEVEL [5:0] If FIFO_INT_E (in INTEN_REG) is set, when FIFO_USED (in
FIFO_STAT_REG) is greater or equal to FIFO_INT_LEVEL, an
interrupt occurs.
0x18
5.1.4 Interrupt Pending Register (INTC_PEND_REG)
Register Address R/W Description Reset Value
INTC_PEND_REG 0x4D40800C R/W Interrupt Pending Register 0x0
Field Bit Description Initial State
Reserved [31] Should be set ‘1’
−
Reserved [30:11] Reserved
−
INTP_CMD_FIN [10] Current Command Finished interrupt flag.
Writing ‘1’ to this bit clears this flag.
−
INTP_ALL_FIN [9] All Commands Finished interrupt flag.
Writing ‘1’ to this bit clears this flag.
−
INTP_FULL [8] Command FIFO Full interrupt flag.
Writing ‘1’ to this bit clears this flag.
−
Reserved [7:1]
− −
INTP_FIFO_LEVEL [0] FIFO_USED reaches FIFO_INT_LEVEL interrupt flag.
Writing ‘1’ to this bit clears this flag.
−