User's Manual

2D S3C2450X RISC MICROPROCESSOR
19-16
5.1 GENERAL REGISTERS
5.1.1 Control Register (CONTROL_REG)
Register Address R/W Description Reset Value
CONTROL_REG 0x4D408000 W Control register 0x0
Field Bit Description Initial State
Reserved [31:1]
−
0x0
R [0] Software Reset
Write to this bit results in a one-cycle reset signal to FIMG2D
graphics engine. Every command register and parameter setting
register will be assigned the “Reset Value”, and the command
FIFO will be cleared.
0x0
5.1.2 Interrupt Enable Register (INTEN_REG)
Register Address R/W Description Reset Value
INTEN_REG 0x4D408004 R/W Interrupt Enable register 0x0
Field Bit Description Initial State
Reserved [31:11]
−
0x0
CCF [10] Current Command Finished interrupt enable.
If this bit is set, when the graphics engine finishes the execution of
current command, an interrupt occurs, and the INTP_CMD_FIN
flag in INTC_PEND_REG will be set.
ACF [9] All Commands Finished interrupt enable.
If this bit is set, when the graphics engine finishes the execution of
all commands in the command FIFO, an interrupt occurs, and the
INTP_ALL_FIN flag in INTC_PEND_REG will be set.
0x0
FIFO_FULL [8] Command FIFO Full interrupt enable.
If this bit is set, when command FIFO is full (32 entries), an
interrupt occurs, and the INTP_FULL flag in the interrupt pending
register (INTC_PEND_REG) will be set.
0x0
Reserved [7:1]
−
0x0
FIFO_INT_E [0] If this bit is set, when the number of entries occupied in command
FIFO is greater or equal to FIFO_INT_LEVEL (in
FIFO_INTC_REG), an interrupt occurs, and the
INTP_FIFO_LEVEL flag in the interrupt pending register
(INTC_PEND_REG) will be set.
0x0