User's Manual

S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE
17-21
8.13 ENDPOINT CONTROL REGISTER (ECR)
The endpoint control register is useful for controlling an endpoint both in normal operation and test case. Putting
an endpoint in specific operation mode can be accomplished through the endpoint control register.
Register Address R/W Description Reset Value
ECR 0x4980_0030 R/W Endpoint Control Register 0x0
ECR Bit R/W Description Initial State
[31:13]
−
Reserved
INPKTHLD [12] R/W The MCU can control Tx FIFO status through this bit. If this
bit is set to one, USB does not send IN data to Host.
0 = The USB can send IN data to Host according to
IN FIFO status(normal operation)
1 = The USB sends NAK handshake to Host
regardless of IN FIFO status.
0
OUTPKTHLD [11] R/W The MCU can control Rx FIFO Status through this bit. If this
bit is set to one, USB does not accept OUT data from Host.
0 = The USB can accept OUT data from Host
according to OUT FIFO status(normal operation)
1 = The USB does not accept OUT data from Host.
0
[10:8]
−
Reserved
DUEN [7] R/W Dual FIFO mode Enable
0 = Dual Disable(Single mode)
1 = Dual Enable
0
FLUSH [6] R/W FIFO Flush
FIFO is flushed when this bit is set to 1.
This bit is automatically cleared after MCU writes 1.
0
[5:2]
−
Reserved
ESS [1] R/W Endpoint Stall Set
ESS is set by the MCU when the MCU intends to send
STALL handshake to Host.
This bit is cleared when the MCU writes 0 in it.
0
IEMS [0] R/W Interrupt Endpoint Mode Set
IEMS determines the transfer type of an endpoint.
0 = Interrupt Transfer mode Disable
1 = Interrupt Transfer mode Enable
0