User's Manual

S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE
17-19
8.12 ENDPOINT STATUS REGISTER (ESR)
The endpoint status register reports current status of an endpoint (except EP0) to the MCU
Register Address R/W Description Reset Value
ESR 0x4980_002C R/W Endpoint status register 0x0
ESR Bit R/W Description Initial State
[31:12] Reserved
FPID [11] R/W First OUT Packet interrupt Disable in OUT DMA operation.
First Received OUT packet generates interrupt if this bit is
disabled and DEN in DMA control register is enabled
0 = Disable
1 = Enable
0
OSD [10] R/C OUT Start DMA Operation.
OSD is set when First OUT packet is received after
Registers related DMA Operation are set.
0
DTCZ [9] R/C DMA Total Count Zero
DTCZ is set when DMA Operation Total Counter reach to 0.
This bit is cleared when the MCU writes 1 on it.
0
SPT [8] R/C Short Packet Received.
SPT informs that OUT endpoint receives short packet during
OUT DMA Operation.
This bit is cleared when the MCU writes 1 on it.
0
DOM [7] R Dual Operation Mode
DOM is set when the max packet size of corresponding
endpoint is equal to a half FIFO size.
This bit is read only.
Endpoint0 does not support dual mode.
0
FFS [6] R/C FIFO Flushed.
FFS informs that FIFO is flushed.
This bit is an interrupt source.
This bit is cleared when the MCU clears FLUSH bit in
Endpoint Control Register.
0
FSC [5] R/C Function Stall Condition.
FSC informs that STALL handshake due to functional stall
condition is sent to Host.
This bit is set when endpoint stall set bit is set by the MCU.
This bit is cleared when the MCU writes 1 on it.
0
LWO [4] R Last Word Odd.
Low informs that the lower byte of last word is only valid.
This bit is automatically cleared after the MCU reads packet
data received Host.
0