User's Manual

S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE
17-15
8.8 SYSTEM CONTROL REGISTER (SCR)
This register enables top-level control of the core. MCU should access this register for controls such as Power
saving mode enable/disable.
Register Address R/W Description Reset Value
SCR 0x4980_0020 R/W System control register 0x0
SCR Bit R/W Description Initial State
[31:15]
−
Reserved
DTZIEN [14] R/W DMA Total Counter Zero Interrupt Enable
0 = Disable
1 = Enable
When set to 1, DMA total counter zero interrupt is
generated.
0
[13]
−
Reserved
DIEN [12] R/W DUAL Interrupt Enable
0 = Disable
1 = Enable
When set to 1, Interrupt is activated until Interrupt source is
cleared.
0
[11:9]
−
Reserved
EIE [8] R/W Error Interrupt Enable
This bit must be set to 1 to enable error interrupt.
0
SPDCEN [7] R/W Speed detection Control Enable
0 = Disable
1 = Enable
0
SPDEN [6] R/W Speed Detect End Interrupt Enable
When set to 1, Speed detection interrupt is generated.
0
[5]
−
Reserved
[4]
−
Should be zero 0
SPDC [3] R/W Speed detection Control
Software can reset Speed detection Logic through this bit.
This bit is used to control speed detection process in case of
System with a long initial time.
0 = Enable
1 = Disable
0
MFRM [2] R/W Resume by MCU
If this bit is set, the suspended core generates a resume
signal. This bit is set when MCU writes 1. This bit is cleared
when MCU writes 0.
0
HSUSPE [1] R/W Suspend Enable
When set to 1, core can respond to the suspend signaling
by USB host.
0
HRESE [0] R/W Reset Enable
When set to 1, core can respond to the reset signaling by
USB host.
0