User's Manual

S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE
17-5
7 USB 2.0 FUNCTION CONTROLLER SPECIAL REGISTERS
The USB 2.0 controller includes several 16-bit registers for the endpoint programming and debugging. The
registers can be grouped into two categories. Few of the indexed registers are related to endpoint 0, but most of
them are utilized for the control and status monitoring of each data endpoint, including FIFO control and packet
size configuration. The buffer register for TX/RX data buffering also belong to the indexed register/
The non-indexed registers are mainly used for the control and status checking of the system. The control and
status registers of endpoint0 belong to these non-indexed registers.
Table 17-1. Non-Indexed Registers
Register Address R/W Description
IR 0x4980_0000 R/W Index Register
EIR 0x4980_0004 R/W Endpoint Interrupt Register
EIER 0x4980_0008 R/W Endpoint Interrupt Enable Register
FAR 0x4980_000C R Function Address Register
EDR 0x4980_0014 R/W Endpoint Direction Register
TR 0x4980_0018 R/W Test Register
SSR 0x4980_001C R/W System Status Register
SCR 0x4980_0020 R/W System Control Register
EP0SR 0x4980_0024 R/W EP0 Status Register
EP0CR 0x4980_0028 R/W EP0 Control Register
EP0BR 0x4980_0060 R/W EP0 Buffer Register
EP1BR 0x4980_0064 R/W EP1 Buffer Register
EP2BR 0x4980_0068 R/W EP2 Buffer Register
EP3BR 0x4980_006C R/W EP3 Buffer Register
EP4BR 0x4980_0070 R/W EP4 Buffer Register
EP5BR 0x4980_0074 R/W EP5 Buffer Register
EP6BR 0x4980_0078 R/W EP6 Buffer Register
EP7BR 0x4980_007C R/W EP7 Buffer Register
EP8BR 0x4980_0080 R/W EP8 Buffer Register
FCON 0x4980_0100 R/W Burst FIFO-DMA Control
FSTAT 0x4980_0104 R/W Burst FIFO status