User's Manual

S3C2450X RISC MICROPROCESSOR UART
15-19
3.7 UART FIFO STATUS REGISTER
There are four UART FIFO status registers including UFSTAT0, UFSTAT1 UFSTAT2 and UFSTAT3 in the UART
block.
Register Address R/W Description Reset Value
UFSTAT0 0x50000018 R UART channel 0 FIFO status register 0x00
UFSTAT1 0x50004018 R UART channel 1 FIFO status register 0x00
UFSTAT2 0x50008018 R UART channel 2 FIFO status register 0x00
UFSTAT3 0x5000C018 R UART channel 3 FIFO status register 0x00
UFSTATn Bit Description Initial State
Reserved [15]
−
0
Tx FIFO Full [14] Set to 1 automatically whenever transmit FIFO is full during
transmit operation
0 = 0-byte ≤ Tx FIFO data ≤ 63-byte
1 = Full
0
Tx FIFO Count [13:8] Number of data in Tx FIFO 0
Reserved [7]
−
0
Rx FIFO Full [6] Set to 1 automatically whenever receive FIFO is full during
receive operation
0 = 0-byte ≤ Rx FIFO data ≤ 63-byte
1 = Full
0
Rx FIFO Count [5:0] Number of data in Rx FIFO 0