User's Manual

UART S3C2450X RISC MICROPROCESSOR
15-16
3.4 UART MODEM CONTROL REGISTER
There are three UART MODEM control registers including UMCON0 and UMCON1 in the UART block.
Register Address R/W Description Reset Value
UMCON0 0x5000000C R/W UART channel 0 Modem control register 0x0
UMCON1 0x5000400C R/W UART channel 1 Modem control register 0x0
UMCON2 0x5000800C R/W UART channel 2 Modem control register 0x0
UMCONn Bit Description Initial State
RTS trigger
Level
[7:5] When AFC bit is enabled, these bits determine when to inactivate
(High) nRTS signal.
000 = When RX FIFO contains 63 bytes.
001 = When RX FIFO contains 56 bytes.
010 = When RX FIFO contains 48 bytes.
011 = When RX FIFO contains 40 bytes.
100 = When RX FIFO contains 32 bytes.
101 = When RX FIFO contains 24 bytes.
110 = When RX FIFO contains 16 bytes.
111 = When RX FIFO contains 8 bytes.
000
Auto Flow
Control (AFC)
[4] 0 = Disable
1 = Enable
0
Reserved [3:1] These bits must be 0's 00
Request to Send [0] If AFC bit is enabled, this value will be ignored. In this case the
S3C2450 will control nRTS automatically.
If AFC bit is disabled, nRTS must be controlled by software.
0 = 'H' level (Inactivate nRTS)
1 = 'L' level (Activate nRTS)
0
NOTES:
1. UART 3 does not support AFC function, because the S3C2450 has no nRTS3 and nCTS3.
2. If AFC bit is enabled and Time-out bit is disabled, RTS trigger level must be lager than Rx FIFO trigger level.
3. Example ) RX interrupt mode, RTS trigger level b101(24byte), RX FIFO trigger level b10(16byte).
This example shows RX FIFO always contains equal or less than 24 bytes.
(have space equal or larger than 40bytes.)
FIFO
contains
FIFO Spare
space
nRTS
signal
Interrupt Note
24 byte
40 byte High -
RTS trigger Level
23 byte
41 byte Low -
…
… Low -
17 byte
47 byte Low -
16 byte
48 byte Low Occur RX FIFO trigger Level
15 byte
49 byte Low -