User's Manual

S3C2450X RISC MICROPROCESSOR UART
15-15
3.3 UART FIFO CONTROL REGISTER
There are four UART FIFO control registers including UFCON0, UFCON1, UFCON2 and UFCON3 in the UART
block.
Register Address R/W Description Reset Value
UFCON0 0x50000008 R/W UART channel 0 FIFO control register 0x0
UFCON1 0x50004008 R/W UART channel 1 FIFO control register 0x0
UFCON2 0x50008008 R/W UART channel 2 FIFO control register 0x0
UFCON3 0x5000C008 R/W UART channel 3 FIFO control register 0x0
UFCONn Bit Description Initial State
Tx FIFO Trigger
Level
(note 2)
[7:6] Determine the trigger level of transmit FIFO.
00 = Empty
01 = 16-byte
10 = 32-byte
11 = 48-byte
00
Rx FIFO Trigger
Level
(note 2)
[5:4] Determine the trigger level of receive FIFO.
00 = 1-byte
01 = 8-byte
10 = 16-byte
11 = 32-byte
00
Reserved [3]
−
0
Tx FIFO Reset [2] Auto-cleared after resetting FIFO
0 = Normal
1 = Tx FIFO reset
0
Rx FIFO Reset [1] Auto-cleared after resetting FIFO
0 = Normal
1 = Rx FIFO reset
0
FIFO Enable
(note 2)
[0]
0 = Disable
(note 1)
1 = Enable
0
NOTES:
1. At DMA mode, FIFO Enable should be Disabled.
2. Please refer the following recommendation for Interrupt / DMA mode.
Mode FIFO enable TX FIFO
Trigger level
RX FIFO
Trigger level
RX time out
enable
Interrupt mode Enable (FIFO mode) 16~48byte 8~32byte enable
DMA mode
Disable (Non-FIFO
mode)
n/a n/a n/a