User's Manual

S3C2450X RISC MICROPROCESSOR UART
15-13
3.2 UART CONTROL REGISTER
There are four UART control registers including UCON0, UCON1, UCON2 and UCON3 in the UART block.
Register Address R/W Description Reset Value
UCON0 0x50000004 R/W UART channel 0 control register 0x00
UCON1 0x50004004 R/W UART channel 1 control register 0x00
UCON2 0x50008004 R/W UART channel 2 control register 0x00
UCON3 0x5000C004 R/W UART channel 3 control register 0x00
UCONn Bit Description Initial State
Clock Selection [11:10] Select PCLK, EXTUARTCLK(External UART clock) or divided
EPLL clock for source clock of the UART.
(note 5)
00, 10
(note 1)
= PCLK
01 = EXTUARTCLK
11 = Divided EPLL clock (Refer to the Clock divider control
register1 (CLKDIV1) in the system controller).
0
Tx Interrupt
Type
[9] Interrupt request type.
0 = Pulse (Interrupt is requested as soon as the Tx buffer
becomes empty in Non-FIFO mode or reaches Tx FIFO Trigger
Level in FIFO mode.)
0
Rx Interrupt
Type
[8] Interrupt request type.
0 = Pulse (Interrupt is requested the instant Rx buffer receives
the data in Non-FIFO mode or reaches Rx FIFO Trigger Level in
FIFO mode.)
0
Rx Time Out
Enable
[7] Enable/Disable Rx time out interrupt when UART FIFO is
enabled. The interrupt is a receive interrupt.
(note 2)
0 = Disable 1 = Enable
0
Rx Error Status
Interrupt Enable
[6] Enable the UART to generate an interrupt upon an exception,
such as a break, frame error, parity error, or overrun error during
a receive operation.
0 = Do not generate receive error status interrupt.
1 = Generate receive error status interrupt.
0
Loopback Mode [5] Setting loopback bit to 1 causes the UART to enter the loopback
mode. This mode is provided for test purposes only.
0 = Normal operation 1 = Loopback mode
0
Send break
signal
[4] Setting this bit causes the UART to send a break during 1 frame
time. This bit is auto-cleared after sending the break signal
0 = Normal transmit 1 = Send break signal
0