User's Manual

xxviii S3C2450X RISC MICROPROCESSOR
List of Tables
Table Title Page
Number Number
1-1 400-Pin FBGA Pin Assignments − Pin Number Order (1/4) ........................................1-7
1-1 400-Pin FBGA Pin Assignments − Pin Number Order (2/4) ........................................1-8
1-1 400-Pin FBGA Pin Assignments − Pin Number Order (3/4) ........................................1-9
1-1 400-Pin FBGA Pin Assignments – Pin Number Order (4/4) ........................................1-10
1-2 S3C2450 400-Pin FBGA Pin Assignments..................................................................1-11
1-3 I/O Cell Types and Descriptions ..................................................................................1-23
1-4 S3C2450 Signal Descriptions ......................................................................................1-24
1-5 S3C2450 Operation Mode Description ........................................................................1-31
1-6 Base Address of Special Registers..............................................................................1-33
1-7 S3C2450 Special Registers .........................................................................................1-34
2-1 Registers & GPIO Status in RESET (R: reset, S: sustain previous value) ..................2-5
2-2 Clock source selection for the main PLL and clock generation logic ..........................2-6
2-3 Clock Source Selection for the EPLL...........................................................................2-7
2-4 PLL & Clock Generator Condition................................................................................2-7
2-5 Clock Division Ratio of MPLL Region ..........................................................................2-10
2-6 ESYSCLK Control ........................................................................................................2-12
2-7 The Status of PLL and ARMCLK After Wake-up .........................................................2-19
2-8 Power Saving Mode Entering/Exiting Condition ..........................................................2-20
2-9 System Controller Address Map ..................................................................................2-21
8-1 Timing Parameter Each PIO Mode ..............................................................................8-7
8-2 Memory Map Table ......................................................................................................8-9
9-1
DMA request sources for each channel.......................................................................9-2
11-1 S3C2450 Port Configuration (Sheet 1) ........................................................................11-2
14-1 RTC Register summary ...............................................................................................14-7
15-1 Example of nRTS signal change by FIFO Spare size
(In case of Reception Case in UART A) ......................................................................15-4
15-2 Interrupts in Connection with FIFO ..............................................................................15-6
15-3 Clock, EPLL Speed Guide ...........................................................................................15-11
15-4 Recommended Value Table of DIVSLOTn Register ...................................................15-23
16-1 OHCI Registers for USB Host Controller .....................................................................16-2