User's Manual

S3C2450X RISC MICROPROCESSOR DMA CONTROLLER
9-17
4.10 DMA REQUESET SELECTION REGISTER (DMAREQSEL)
Register Address R/W Description Reset Value
DMAREQSEL0 0x4B000024 R/W DMA0 Request Selection Register 000
DMAREQSEL1 0x4B000124 R/W DMA1 Request Selection Register 000
DMAREQSEL2 0x4B000224 R/W DMA2 Request Selection Register 000
DMAREQSEL3 0x4B000324 R/W DMA3 Request Selection Register 000
DMAREQSEL4 0x4B000424 R/W DMA4 Request Selection Register 000
DMAREQSEL5 0x4B000524 R/W DMA5 Request Selection Register 000
DMAREQSEL6 0x4B000624 R/W DMA6 Request Selection Register 000
DMAREQSEL7 0x4B000724 R/W DMA7 Request Selection Register 000
DMAREQSELn Bit Description Initial State
HWSRCSEL [5:1] Select DMA request source for each DMA.
→ Refer to the Table 11-1 on page 11-2.
This bits control the 8-1 MUX to select the DMA request source of
each DMA. These bits have meanings if and only if H/W request
mode is selected by DMAREQSELn[0].
00000
SWHW_SEL [0] Select the DMA source between software (S/W request mode) and
hardware (H/W request mode).
0 = S/W request mode is selected and DMA is triggered by setting
SW_TRIG bit of DMASKTRIG control register.
1 = DMA source selected by bit [5:1] is used to trigger the DMA
operation.
0