User's Manual

DMA CONTROLLER S3C2450X RISC MICROPROCESSOR
9-12
4.5 DMA CONTROL REGISTER (DCON)
Register Address R/W Description Reset Value
DCON0 0x4B000010 R/W DMA0 Control Register 0x00000000
DCON1 0x4B000110 R/W DMA1 Control Register 0x00000000
DCON2 0x4B000210 R/W DMA2 Control Register 0x00000000
DCON3 0x4B000310 R/W DMA3 Control Register 0x00000000
DCON4 0x4B000410 R/W DMA4 Control Register 0x00000000
DCON5 0x4B000510 R/W DMA5 Control Register 0x00000000
DCON6 0x4B000610 R/W DMA6 Control Register 0x00000000
DCON7 0x4B000710 R/W DMA7 Control Register 0x00000000
DCONn Bit Description Initial State
DMD_HS [31] Select one between demand mode and handshake mode.
0 = demand mode is selected
1 = handshake mode is selected.
In both modes, DMA controller starts its transfer and asserts DACK
for a given asserted DREQ. The difference between two modes is
whether it waits for the de-asserted DACK or not. In handshake
mode, DMA controller waits for the de-asserted DREQ before
starting a new transfer. If it sees the de-asserted DREQ, it de-
asserts DACK and waits for another asserted DREQ. In contrast, in
the demand mode, DMA controller does not wait until the DREQ is
de-asserted. It just de-asserts DACK and then starts another
transfer if DREQ is asserted. We recommend using handshake
mode for external DMA request sources to prevent unintended
starts of new transfers.
0
SYNC [30] Select DREQ/DACK synchronization.
0 = DREQ and DACK are synchronized to PCLK (APB clock).
1 = DREQ and DACK are synchronized to HCLK (AHB clock).
Therefore, devices attached to AHB system bus, this bit has to be
set to 1, while those attached to APB system, it should be set to 0.
For the devices attached to external system, user should select this
bit depending on whether the external system is synchronized with
AHB system or APB system.
0
INT [29] Enable/Disable the interrupt setting for CURR_TC(terminal count)
0 = CURR_TC interrupt is disabled. User has to look the transfer
count in the status register. (i.e., polling)
1 = Interrupt request is generated when all the transfer is done (i.e.,
CURR_TC becomes 0).
0
TSZ [28] Select the transfer size of an atomic transfer (i.e., transfer
performed at each time DMA owns the bus before releasing the
bus).
0 = A unit transfer is performed.
1 = A burst transfer of length four is performed.
0