User's Manual

S3C2450X RISC MICROPROCESSOR DMA CONTROLLER
9-11
4.4 DMA INITIAL DESTINATION CONTROL REGISTER (DIDSTC)
Register Address R/W Description Reset Value
DIDSTC0 0x4B00000C R/W DMA0 Initial Destination Control Register 0x00000000
DIDSTC1 0x4B00010C R/W DMA1 Initial Destination Control Register 0x00000000
DIDSTC2 0x4B00020C R/W DMA2 Initial Destination Control Register 0x00000000
DIDSTC3 0x4B00030C R/W DMA3 Initial Destination Control Register 0x00000000
DIDSTC4 0x4B00040C R/W DMA4 Initial Destination Control Register 0x00000000
DIDSTC5 0x4B00050C R/W DMA5 Initial Destination Control Register 0x00000000
DIDSTC6 0x4B00060C R/W DMA6 Initial Destination Control Register 0x00000000
DIDSTC7 0x4B00070C R/W DMA7 Initial Destination Control Register 0x00000000
DIDSTn Bit Description Initial State
CHK_INT [2] Select interrupt occurrence time when auto reload is setting
0 = Interrupt will occur when TC reaches 0.
1 = Interrupt will occur after auto-reload is performed
0
LOC [1] Bit 1 is used to select the location of destination.
0 = The destination is in the system bus (AHB).
1 = The destination is in the peripheral bus (APB).
0
INC [0] Bit 0 is used to select the address increment.
0 = Increment
1 = Fixed
If it is 0, the address is increased by its data size after each transfer
in burst and single transfer mode.
If it is 1, the address is not changed after the transfer (In the burst
mode, address is increased during the burst transfer, but the
address is recovered to its first value after the transfer).
0