Manualshelf

User's Manual

ManualsBrandsDiasonic Technology ManualsElectronicsTOUCH SCREEN MONITOR
21222324252627282930
Table Of Contents
S3C2450X RISC MICROPROCESSOR xxi
List of Figures
Figure Title Page
Number Number
1-1 S3C2450 Block Diagram ............................................................................................. 1-5
1-2 S3C2450 Pin Assignments (400-FBGA) Top view...................................................... 1-6
1-3 Memory Map................................................................................................................ 1-32
2-1 System Controller Block Diagram................................................................................ 2-2
2-2 Power-On Reset Sequence......................................................................................... 2-4
2-3 Clock Generator Block Diagram..................................................................................2-6
2-4 Main Oscillator Circuit Examples................................................................................. 2-7
2-5 PLL(Phase-Locked Loop) Block Diagram ...................................................................2-8
2-6 The Case that Changes Slow Clock by Setting PMS Value........................................ 2-8
2-7 The Clock Distribution Block Diagram......................................................................... 2-9
2-8 MPLL Based Clock Domain......................................................................................... 2-9
2-9 EPLL Based Clock Domain ......................................................................................... 2-12
2-10 Power Mode State Diagram......................................................................................... 2-13
2-11 Entering STOP Mode and Exiting STOP Mode (wake-up).......................................... 2-17
2-12 Entering SLEEP Mode and Exiting SLEEP Mode (wake-up)......................................2-18
2-13 Usage of PWROFF_SLP ............................................................................................. 2-34
3-1 The Configuration of MATRIX and Memory Sub-System of S3C2450 ....................... 3-1
5-1 SMC Block Diagram .................................................................................................... 5-3
5-2 SMC Core Block Diagram............................................................................................ 5-3
5-3 External Memory Two Output Enable Delay State Read ............................................ 5-4
5-4 Read Timing Diagram (DRnCS = 1, DRnOWE = 0).................................................... 5-4
5-5 Read Timing Diagram (DRnCS = 1, DRnOWE = 1).................................................... 5-5
5-6
External Burst ROM with WSTRD=
2 and WSTBRD=1 Fixed Length Burst Read...... 5-6
5-7 External Synchronous Fixed Length Four Transfer Burst Read ................................. 5-7
5-8 External Memory Two Write Enable Delay State Write............................................... 5-8
5-9 Write Timing Diagram (DRnCS = 1, DRnOWE = 0) .................................................... 5-9
5-10 Write Timing Diagram (DRnCS = 1, DRnOWE = 1) .................................................... 5-9
5-11 Synchronous Two Wait State Write............................................................................. 5-10
5-12 Read, then two Writes (WSTRD=WSTWR=0), Two Turnaround Cycles (IDCY=2) ... 5-11
5-13 Memory Interface with 8-bit SRAM (2MB) ................................................................... 5-13
5-14 Memory Interface with 16-bit SRAM (4MB) ................................................................. 5-13
6-1 Mobile DRAM Controller Block Diagram ..................................................................... 6-2
6-2 Memory Interface with 16-bit SDRAM (4Mx16, 4banks) ............................................. 6-4
6-3 Memory Interface with 32-bit SDRAM (4Mx16 * 2ea, 4banks).................................... 6-4
6-4 Memory Interface with 16-bit Mobile DDR and DDR2................................................. 6-5
6-5 DRAM Timing Diagram................................................................................................ 6-6
6-6 CL (CAS Latency) Timing Diagram .............................................................................6-6
6-7 t
ARFC
Timing Diagram.................................................................................................. 6-7