User's Manual

CF CONTROLLER S3C2450X RISC MICROPROCESSOR
8-20
2.13 ATA_CFG REGISTER
Register Address R/W Description Reset Value
ATA_CFG 0x4B801918 R/W ATA Configuration register 0x0000_0000
ATA_CFG Bits Description R/W Reset Value
Reserved [31:9] Reserved bits R 0x0
sbuf_empty_
mode
[8] Determines whether to continue automatically when
source buffer is empty. This bit should not be changed
during runtime operation.
0 = Continue automatically with new source buffer
address.
1 = Stay in pause state and wait for CPU’s action.
** With the sbuf_empty mode is "0" and the transmission
data size is bigger than the source buffer size, the source
buffer empty interrupt(sbuf_empty_int) happens before
setting of the second source buffer base address and size.
Then ATA host controller brings data from the first source
buffer repeatedly. To avoid this, after 1st source buffer is
empty, the “sbuf_empty_mode” bit automatically goes to
HIGH even though the default is “0”. So user must make a
command “CONTINUE”. And then user don’t want that the
CPU dose not interfere the change of the next source
buffer address, set “0” at the bit 8 before/after the next
base address and size.
R/W 0x0
tbuf_full_mode [7] Determines whether to continue automatically when track
buffer is full. This bit should not be changed during runtime
operation.
0 = Continue automatically with new track buffer address.
1 = Stay in pause state and wait for CPU’s action.
** With the tbuf_full mode is "0" and the transmission data
size is bigger than the target buffer size, the target buffer
full interrupt(tbuf_full_int) happens before setting of the
second target buffer base address and size. Then ATA
host controller sends data to the first target buffer
repeatedly. To avoid this, after 1st target buffer is full, the
“tbuf_buf_mode” bit automatically goes to HIGH even
though the default is “0”. So user must make a command
“CONTINUE”. And then user don’t want that the CPU dose
not interfere the change of the next target buffer address,
set “0” at the bit 8 before/after the next base address and
size.
R/W 0x0
byte_swap [6] Determines whether data endian is little or big in 16bit
data.
0 = Little endian ( data[15:8], data[7:0] )
1 = Big endian ( data[7:0], data[15:8] )
R/W 0x0
atadev_irq_al [5] Device interrupt signal level
0 = Active high
R/W 0x0