User's Manual

CF CONTROLLER S3C2450X RISC MICROPROCESSOR
8-18
2.10 ATA_SWRST REGISTER
Register Address R/W Description Reset Value
ATA_SWRST 0x4B80190C R/W ATA S/W RESET register 0x0000_0000
ATA_SWRST Bits Description R/W Reset Value
Reserved [31:1] Reserved bits R 0x0
ata_swrstn [0] Software reset for the ATA host
0 = No reset
1 = Software reset for all ATA host module.
After software reset, to continue transfer, user must
configure all registers of host controller and device
registers.
R/W 0x0
2.11 ATA_IRQ REGISTER
Register Address R/W Description Reset Value
ATA_IRQ 0x4B801910 R/W ATA IRQ register 0x0000_0000
ATA_IRQ Bits Description R/W Reset Value
Reserved [31:5] Reserved bits R 0x0
sbuf_empty_int [4] When source buffer is empty.
CPU can clear this interrupt by writing “1”.
R/W 0x0
tbuf_full_int [3] When track buffer is half full.
CPU can clear this interrupt by writing “1”.
R/W 0x0
atadev_irq_int [2] When ATA device generates interrupt.
CPU can clear this interrupt by writing “1”.
R/W 0x0
reserved [1] reserved R/W 0x0
xfr_done_int [0] When all data transfers are finished.
CPU can clear this interrupt by writing “1”.
R/W 0x0