User's Manual

S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER
7-15
13.3 CONTROL REGISTER
Register Address R/W Description Reset Value
NFCONT 0x4E000004 R/W NAND Flash control register 0x000100C6
NFCONT Bit Description Initial State
Reserved [31:19] Reserved 0
ECC Direction [18] 4-bit, 8-bitECC encoding / decoding control
0 = Decoding 4-bit, 8bit ECC, It is used for page read
1 = Encoding 4-bit, 8-bit ECC, It is be used for page program
0
Lock-tight [17] Lock-tight configuration
0 = Disable lock-tight
1 = Enable lock-tight,
Once this bit is set to 1, you cannot clear. Only reset or wake
up from sleep mode can make this bit disable (cannot
cleared by software).
When it is set to 1, the area setting in NFSBLK
(0x4E000020) to NFEBLK (0x4E000024) is unlocked, and
except this area, write or erase command will be invalid and
only read command is valid.
When you try to write or erase locked area, the illegal
access will be occurred (NFSTAT [5] bit will be set).
If the NFSBLK and NFEBLK are same, entire area will be
locked.
0
Soft Lock [16] Soft Lock configuration
0 = Disable lock
1 = Enable lock
Soft lock area can be modified at any time by software.
When it is set to 1, the area setting in NFSBLK
(0x4E000020) to NFEBLK (0x4E000024) is unlocked, and
except this area, write or erase command will be invalid and
only read command is valid.
When you try to write or erase locked area, the illegal
access will be occurred (NFSTAT [5] bit will be set).
If the NFSBLK and NFEBLK are same, entire area will be
locked.
1
Reserved [15:13] Reserved. Should be written to 0. 000
EnbECCDecINT [12] 4-bit, 8-bit ECC decoding completion interrupt control
0 = Disable interrupt
1 = Enable interrupt
0
8bit Stop [11] 8-bit ECC encoding/decoding operation initialization 0