User's Manual

MOBILE DRAM CONTROLLER S3C2450X RISC MICROPROCESSOR
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3.7 MOBILE DRAM REFRESH CONTROL REGISTER
Register Address R/W Description Reset Value
REFRESH 0x48000010 R/W Mobile DRAM refresh control register 0x0000_0020
REFRESH Bit Description Initial State
Reserved [31:16] Reserved 0x0000
REFCYC [15:0]
DRAM refresh cycle.
Example: Refresh period is 15.6us, and HCLK is 66MHz. The
value of REFCYC is as follows:
REFCYC = 15.6 x 10
-6
x 66 x 10
6
= 1029
0x0020
3.8 MOBILE DRAM WRITE BUFFER TIME OUT REGISTER
A write to a enabling write buffer loads the value in the timeout register into timeout down counter of the buffer.
When the timeout counter reached 0 the contents of write buffer is flushed to the external DRAM. The down
counter is clocked HCLK. Writing a value of 0 in the TIMEOUT register disables the write buffer timeout function.
Register Address R/W Description Reset Value
TIMEOUT 0x48000014 R/W Write Buffer Time out control register 0x0000_0000
TIMEOUT Bit Description Initial State
Reserved [31:16] Reserved 0x0000
TIMEOUT [15:0] Write buffer time-out delay time 0x0000