User's Manual

S3C2450X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER
6-11
3.6 MOBILE DRAM (EXTENDED ) MODE REGISTER SET REGISTER
Register Address R/W Description Reset Value
BANKCON3 0x4800000C R/W Mobile DRAM (E)MRS Register 0x8000_0003
3.6.1 mSDRAM / mDDR
PnBANKCON Bit Description Initial State
BA [31:30] Bank address for EMRS 10b
Reserved [29:23] Should be ‘0’ 0000000b
DS [22:21] DS(Driver Strength) for EMRS 00b
Reserved [20:19] Should be ‘0’ 00b
PASR [18:16] PASR(Partial Array Self Refresh) for EMRS 000b
BA [15:14] Bank address for MRS 0b
Reserved [15:7] Should be ‘0’ 000000000b
CAS Latency [6:4]
CAS Latency for MRS
00 = Reserved
01 = 1-clock
10 = 2-clock
11 = 3-clock
000b
Burst Type [3]
DRAM Burst Type (Read Only)
Only support sequential burst type.
0b
Burst Length [2:0]
DRAM Burst Length (Read Only)
This value is determined internally.
011b
NOTE: Bit[15:0] is used for MRS command cycle, and Bit[31:16] is for EMRS command cycle. You can program this register
as memory type you are using. Each 16-bit exactly map the (E)MRS register bit location. Refer to memory data sheet.