User's Manual

MOBILE DRAM CONTROLLER S3C2450X RISC MICROPROCESSOR
6-10
3.5 MOBILE DRAM TIMMING CONTROL REGISTER
Register Address R/W Description Reset Value
BANKCON2 0x48000008 R/W Mobile DRAM timing control register 0x0099_003F
TIMECON Bit Description Initial State
Reserved [31:24] Reserved 0x00
tRAS [23:20]
Row active time
0000 = 1-clock 0001 = 2-clock 0010 = 3-clock 0011 = 4-clock
0100 = 5-clock 0101 = 6-clock 0110 = 7-clock 0111 = 8-clock
1000 = 9-clock 1001 = 10-clock 1010 = 11-clock 1011 = 12-clock
1100 = 13-clock 1101 = 14-clock 1110 = 15-clock 1111 = 16-clock
1001b
tARFC [19:16]
Self-refresh or Auto-refresh to next command cycle time
0000 = 1-clock 0001 = 2-clock 0010 = 3-clock 0011 = 4-clock
0100 = 5-clock 0101 = 6-clock 0110 = 7-clock 0111 = 8-clock
1000 = 9-clock 1001 = 10-clock 1010 = 11-clock 1011 = 12-clock
1100 = 13-clock 1101 = 14-clock 1110 = 15-clock 1111 = 16-clock
1001b
Reserved [15:6] Reserved 0x000
CAS Latency
[5:4] CAS Latency Control
00 = Reserved
01 = 1-clock
10 = 2-clock
11 = 3-clock
011b
tRCD [3:2]
RAS to CAS delay
00 = 1-clock
01 = 2-clock
10 = 3-clock
11 = 4-clock
11b
tRP [1:0]
Row pre-charge time
00 = 1-clock
01 = 2-clock
10 = 3-clock
11 = 4-clock
11b