User's Manual

S3C2450X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER
6-9
3.4 MOBILE DRAM CONTROL REGISTER
Register Address R/W Description Reset Value
BANKCON1 0x48000004 R/W Mobile DRAM control register 0x4400_0040
BANKCON Bit Description Initial State
BUSY [31]
DRAM controller status bit (read only)
0 = IDLE
1 = BUSY
0b
DQSInDLL
*
[30:28]
DQSIn Delay selection
Should be set ‘3’
100b
Reserved [27:26] Should be ‘1’ 01b
Reserved [25:8] Should be ‘1’ 0
BStop [7]
Read Burst stop control
0 = Not support Read Burst Stop
1 = Support Read Burst Stop
Note: This function is only valid in mDDR interface.
0b
WBUF [6]
Write buffer control
0 = Disable
1 = Enable
Note: Disabling the write buffer will flush any stored values to the
external DRAM memory.
1b
AP [5]
Auto pre-charge control
0 = Enable auto pre-charge
1 = Disable auto pre-charge
Note: If PWRDN is enabled, then AP=0 provides pre-charge power
down and AP=1 provides active power down.
0b
PWRDN [4]
0 = Not support DRAM power down control
1 = Support DRAM power down control
0b
Reserved [3:2] Reserved 00b
INIT [1:0]
DRAM initialization control
00 = Normal operation
01 = Issue PALL command
10 = Issue MRS command
11 = Issue EMRS command
00b