User's Manual

STATIC MEMORY CONTROLLER S3C2450X RISC MICROPROCESSOR
5-20
4.9 SMC CONTROL REGISTER
Register Address R/W Description Reset Value
SMCCR 0x4F000204 R/W SMC control register 0x3
Bit Description Initial State
[31:2] Read undefined. Write as zero. 0x0
MemClkRatio [1] Defines the ratio of SMCLK to HCLK:
0 = SMCLK = HCLK.
1 = SMCLK = HCLK/2.
0x1
SMClockEn [0] SMCLK enable:
0 = Clock only active during memory accesses.
1 = Clock always running.
Clock stopping saves power by stopping SMCLK when it is
not required. If clock stopping is enabled before the memory
access, the SMC stops SMCLK on the following conditions:
• asynchronous read access to asynchronous memory
• asynchronous write access to asynchronous memory
• asynchronous read access to synchronous memory
• asynchronous write access to synchronous memory.
0x1