User's Manual

S3C2450X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER
5-17
4.6 BANK CONTROL REGISTERS 0-5
Register Address R/W Description Reset Value
SMBCR0
0x4F000014 R/W Bank0 control register See note in p5-17
SMBCR1
0x4F000034 R/W Bank1 control register 0x303000
SMBCR2
0x4F000054 R/W Bank2 control register 0x303010
SMBCR3
0x4F000074 R/W Bank3 control register 0x303000
SMBCR4
0x4F000094 R/W Bank4 control register 0x303010
SMBCR5
0x4F0000B4 R/W Bank5 control register 0x303010
Bit Description Initial State
[31:26] Read undefined. Write as zero. 0x0
DELAYnCS [25:22] Controls the delay between ADDR signal and nCS signal. The
field is valid only when DRnCS bit is 1.
0x0
[21] not available(should be high) 0x1
AddrValid
WriteEn
[20] Controls the behavior of the signal RSMAVD during write
operations:
0 = Signal always HIGH
1 = Signal active for asynchronous and synchronous write
accesses (default).
0x1
BurstLenWrite [19:18] Burst transfer length. Sets the number of sequential transfers
that the burst device supports for a write:
00 = 4-transfer burst (default)
01 = Reserved
10 = Reserved
11 = Reserved
0x0
SyncWriteDev [17] 0 = Asynchronous device (default).
1 = Synchronous device.
0x0
BMWrite [16] Burst mode write:
0 = Nonburst writes to memory devices (default at reset)
1 = Burst mode writes to memory devices.
0x0
DRnOWE [15]
0 = No delay (default)
1 = Get the delay between nCS signal and nOE/nWE signal.
nOE: The number of cycle is defined by SMBWSTOENRx
which must be larger than 1.
nWE: The number of cycle is defined by SMBWSTWENRx
which must be larger than 1.
This bit is applied only when nWAIT signal is used.
0x0
Reserved [14] Reserved 0x0
Reserved [13] not available(should be high) 0x1
AddrValid
ReadEn
[12] Controls the behavior of the signal RSMAVD during read
operations:
0 = Signal always HIGH.
1 = Signal active for asynchronous and synchronous read
accesses (default).
0x1