User's Manual

S3C2450X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER
5-15
4.3 BANK WRITE WAIT STATE CONTROL REGISTERS 0-5
Register Address R/W Description Reset Value
SMBWSTWRR0 0x4F000008 R/W Bank0 write wait state control register 0x1F
SMBWSTWRR1 0x4F000028 R/W Bank1 write wait state control register 0x1F
SMBWSTWRR2 0x4F000048 R/W Bank2 write wait state control register 0x1F
SMBWSTWRR3 0x4F000068 R/W Bank3 write wait state control register 0x1F
SMBWSTWRR4 0x4F000088 R/W Bank4 write wait state control register 0x1F
SMBWSTWRR5 0x4F0000A8 R/W Bank5 write wait state control register 0x1F
Bit Description Initial State
[31:5] Read undefined. Write as zero. 0x0
WSTWR [4:0] Write wait state. Defaults to 11111 at reset.
For SRAM , the WSTWR field controls the number of wait states
for write accesses, and the external wait assertion timing for
writes.
Wait state time = WSTWR x SMCLK period
WSTWR does not apply to read-only devices such as ROM.
0x1F
4.4 BANK OUTPUT ENABLE ASSERTION DELAY CONTROL REGISTERS 0-5
Register Address R/W Description Reset Value
SMBWSTOENR0 0x4F00000C R/W Bank0 output enable assertion delay control register 0x2
SMBWSTOENR1 0x4F00002C R/W Bank1 output enable assertion delay control register 0x2
SMBWSTOENR2 0x4F00004C R/W Bank2 output enable assertion delay control register 0x2
SMBWSTOENR3 0x4F00006C R/W Bank3 output enable assertion delay control register 0x2
SMBWSTOENR4 0x4F00008C R/W Bank4 output enable assertion delay control register 0x2
SMBWSTOENR5 0x4F0000A
C
R/W Bank5 output enable assertion delay control register 0x2
Bit Description Initial State
[31:4] Read undefined. Write as zero. 0x0
WSTOEN [3:0] Output enable assertion delay from chip select assertion.
Default to 0x2 at reset
0x2
NOTE: If you would use a muxed OneNAND, the regiseter value of WSTOEN should be larger than 2.