User's Manual

STATIC MEMORY CONTROLLER S3C2450X RISC MICROPROCESSOR
5-14
4 SPECIAL REGISTERS
4.1 BANK IDLE CYCLE CONTROL REGISTERS 0-5
Register Address R/W Description Reset Value
SMBIDCYR0 0x4F000000 R/W Bank0 idle cycle control register 0xF
SMBIDCYR1 0x4F000020 R/W Bank1 idle cycle control register 0xF
SMBIDCYR2 0x4F000040 R/W Bank2 idle cycle control register 0xF
SMBIDCYR3 0x4F000060 R/W Bank3 idle cycle control register 0xF
SMBIDCYR4 0x4F000080 R/W Bank4 idle cycle control register 0xF
SMBIDCYR5 0x4F0000A0 R/W Bank5 idle cycle control register 0xF
Bit Description Initial State
[31:4] Read undefined. Write as zero. 0x0
IDCY [3:0] Idle or turnaround cycles. Default to 1111 at reset.
This field controls the number of bus turnaround cycles added
between read and write accesses to prevent bus contention on
the external memory data bus.
Turnaround time = IDCY x SMCLK period
0xF
4.2 BANK READ WAIT STATE CONTROL REGISTERS 0-5
Register Address R/W Description Reset Value
SMBWSTRDR0 0x4F000004 R/W Bank0 read wait state control register 0x1F
SMBWSTRDR1 0x4F000024 R/W Bank1 read wait state control register 0x1F
SMBWSTRDR2 0x4F000044 R/W Bank2 read wait state control register 0x1F
SMBWSTRDR3 0x4F000064 R/W Bank3 read wait state control register 0x1F
SMBWSTRDR4 0x4F000084 R/W Bank4 read wait state control register 0x1F
SMBWSTRDR5 0x4F0000A4 R/W Bank5 read wait state control register 0x1F
Bit Description Initial State
[31:5] Read undefined. Write as zero. 0x0
WSTRD [4:0] Read wait state. Defaults to 11111 at reset.
For SRAM and ROM, the wSTRD field controls the number of
wait states for read accesses, and the external wait assertion
timing for reads.
For burst ROM, the WSTRD field controls the number of wait
states for the first read access only.
Wait state time = WSTRD x SMCLK period
0x1F