User's Manual

S3C2450X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER
5-7
3.3 SYNCHRONOUS READ/SYNCHRONOUS BURST READ
Single synchronous read operations have the same control signal timing as an asynchronous read operation, but
with different timing requirements for setup and hold relative to the clock. Because the output signals of the SMC
are generated internally from clocked logic, the timing for single synchronous reads is the same as for
asynchronous reads.
Synchronous burst read transfers are performed differently to asynchronous burst reads, because of the internal
address incrementing performed by synchronous burst devices. The PADDR outputs are held with the initial
address value, and the PSMAVD output is asserted during the transfer to indicate that the address is valid.
Four, eight, or continuous synchronous burst lengths are supported, and are controlled by the BurstLenRead bits
in the Bank Control Register SMBCRx when the SyncEnRead and BMRead bits indicate that the device supports
synchronous bursts.
Figure 5-7 shows continuous burst read transfers, where WSTRD = 3 and WSTBRD = 0.
Synchronous Burst READ
SMCLK
ADDR
DATA(IN)
nCS
nOE
SMAVD
D(A)
D(A+4) D(A+8)
D(A+C)
A
WSTRD=3
Figure 5-7. External Synchronous Fixed Length Four Transfer Burst Read