User's Manual

SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR
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8.9 USB PHY CONTROL REGISTER (PHYCTRL)
Register Address R/W Description Reset Value
PHYCTRL 0x4C00_0080 R/W USB2.0 PHY Control Register 0x0000_0000
PHYCTRL Bit Description Initial State
RESERVED [31:6] - 0
CLK_ON_OFF [5] Clock input on off control at pad input area
Should be use with EXT_CLK [2].
When Combination of [5],[2] bit is 2’b11 , could be off clock
input.
00 = Crystal Enable,
01 = Oscillator Enable,
11 = Crystal/Oscillator Disable(PAD Disable),
10 = reserved
0
CLK_SEL [4:3] Reference Clock Frequency Select
00 = 48MHz
01 = Reserved
10 = 12MHz
11 = 24MHz
2’b00
EXT_CLK [2] Clock Select
0 = Crystal
1 = Oscillator
0
INT_PLL_SEL [1] Host 1.1 uses which PLL Clock (48MHz)
0 = use EPLL
(USBHOSTCLK should be 48MHz and The CLK_SEL[1:0]
must be set to 2’b00)
1 = use USB own Internal PLL Clock
0
DOWNSTREAM_
PORT
[0] Downstream Port Select
0 = Device (Function) Mode
1 = Host Mode
0