User's Manual

S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER
2-33
8.4 RESET CONTROL REGISTERS (SWRST AND RSTCON)
Software can reset S3C2450 using SWRST register. The waveform of the reset signals are determined by
RSTCON register.
Register Address R/W Description Reset Value
SWRST 0x4C00_0044 R/W Software reset control register 0x0000_0000
RSTCON 0x4C00_0064 R/W Reset control register 0x0006_0101
When software write the predefined value, 0x533C2450, into SWRST register, then the system controller asserts
internal reset signal and initializes internal state.
SWRST Bit Description Initial Value
SWRST [31:0] If this field has 0x533C2450, then the system will restart. 0x0000_0000
RSTCON register controls the duration of the system reset signal.
RSTCON Bit Description Initial Value
RESERVED [31:19] - 0x0000
RESERVED [18:17] Should be set ‘0x3’ 0x3
PWROFF_SLP [16]
Power Control on pad retention cell I/O.
Retention cell I/O’s power will be off when sleep mode, but
when wakeup process starts, User should write ‘1’ to produce
power on retention I/O (see below detailed description)
1 = set automatically when sleep mode.
0 = cleared by user writing ‘1’
0
RSTCNT [15:8]
Only watch dog and software reset can start counter which is
counted from RSTCNT value. This RSTCNT value effects
delay of releasing reset. After this counter expired, internal
reset (like HRESETn) will be HIGH state.
Range which user can configure is from 0x01 to 0xFE.
(Don’t write 0xFF to this field)
0x01
PWRSETCNT [7:0]
This field configures value of Power Settle Down Counter.
Only When waking up from sleep mode, Power Settle Down
Counter starts counting to wait for stability of external voltage
source. As soon as counter reaches PWRSETCNT value, the
system escapes from sleep mode.
Range which user can configure is from 0x01 to 0xFE.
(Don’t write 0xFF to this field)
Real count number = (PWRSETCNT[7:0] + 1) * 2048
0x01