User's Manual

SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR
2-30
The special clocks are controlled by SCLKCON register. Some blocks in the device require several operating
frequencies, i.e., 48 MHz and 24 MHz for USB interface block. Thus, these output frequencies can be controlled
by the CLKDIV values.
SCLKCON Bit Description
Initial
Value
RESERVED [31:21] - 0x7FF
SPICLK_MPLL1 [20] Enable SPICLK1 (MPLL) 1
SPICLK_MPLL0 [19] Enable SPICLK0 (MPLL) 1
PCM1_EXT [18] Enable PCM1 External Clock 1
PCM0_EXT [17] Enable PCM0 External Clock 1
DDRCLK(Hx2CLK) [16] Enable DDRCLK 1
SSMCCLK(HX1_2CLK) [15] Enable SSMCCLK 1
SPICLK_0 [14] Enable HS-SPI_0 (EPLL) clock 1
HSMMCCLK_EXT [13]
Enable HSMMC_EXT clock for HSMMC0, 1 (EXTCLK)
Reference clock of MPLL
0
HSMMCCLK_1 [12]
Enable HSMMC1_1 clock for
(from EPLL or USB48M output)
1
CAMCLK [11] Enable CAM clock 1
DISPCLK [10] Enable display controller clock 1
I2SCLK_0 [9] Enable I2S_0 clock 1
UARTCLK [8] Enable UART clock 1
SPICLK_1 [7] Enable HS-SPI_1 (EPLL) clock 1
HSMMCCLK_0 [6]
Enable HSMMC_0 clock for
(from EPLL or USB48M output)
1
I2SCLK_1 [5] Enable I2S_1 clock 1
RESERVED [4:2] - 0x7
USB HOST [1] Enable USB HOST clock 1
RESERVED [0] - 1