User's Manual

SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR
2-28
CLKDIV1 configures the clock ratio related on EPLL.
CLKDIV1 Bit Description Initial Value
RESERVED [31:30] - 0
CAMDIV [29:26]
CAM clock divider ratio.
ratio = CAMDIV + 1
0x0
SPIDIV_0 [25:24] HS-SPI clock divider ratio, ratio = (SPIDIV +1) 0x0
DISPDIV [23:16]
Display controller clock divider ratio,
ratio = (DISPDIV + 1)
0x0
I2SDIV_0 [15:12] I2S0 clock divider ratio, ratio = (I2SDIV_0 + 1) 0x0
UARTDIV [11:8] UART clock divider ratio, ratio = (UARTDIV + 1) 0x0
HSMMCDIV_1 [7:6] HSMMC_1 clock divider ratio, ratio = (HSMMCDIV_1 + 1) 0x0
USBHOSTDIV [5:4] Usb Host clock divider ratio, ratio = (USBHOSTDIV + 1) 0x0
RESERVED [3:0] - 0
CLKDIV2 configures the clock ratio related on EPLL or MPLL.
CLKDIV2 Bit Description Initial Value
RESERVED [31:26] - 0
SPIDIV1_EPLL [25:24] HS-SPI_1 clock divider ratio(EPLL), ratio = (SPIDIV_1 +1) 0x0
RESERVED [23:21] - 0
SPIDIV1_MPLL [20:16] HS-SPI1 clock divider ratio(MPLL), ratio = (SPIDIV_1 +1) 0
I2SDIV_1 [15:12] I2S1 clock divider ratio(EPLL), ratio = (I2SDIV_1 + 1) 0x0
RESERVED [11:8] - 0
HSMMCDIV_0 [7:6] HSMMC_0 clock divider ratio(EPLL), ratio = (HSMMCDIV_1 + 1) 0x0
RESERVED [5] - 0
SPIDIV0_MPLL [4:0] HS-SPI0 clock divider ratio(MPLL), ratio = (SPIDIV_1 +1) 0