User's Manual

S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER
2-27
The CLKDIV0 configures the division ratio of each clock generator. The operating speed of ARM can be slow to
reduce the overall power dissipation, if software doest not require full operating performance. In this case, the
power dissipation due to the ARM core can be reduced if the DVS field is ON. The set of DVS field makes that the
operating frequency of ARM is the same as system operating clock (HCLK).
CLKDIV0 Bit Description Initial Value
RESERVED [31:14] -
0x0
DVS [13]
Enable/disable DVS (Dynamic Voltage Scaling) feature
0 = Disable
1 = Enable (The frequency of ARMCLK is the same frequency of
HCLK regardless of ARMDIV field.)
0
RESERVED [12] - 0
ARMDIV [11:9]
ARM clock divider ratio
ARMDIV values are recommended as below.
1/1 = 3'b000
1/2 = 3'b001
1/3 = 3'b010
1/4 = 3'b011
1/6 = 3'b101
1/8 = 3'b111
0x0
EXTDIV [8:6]
External clock divider ratio
ratio = (MPLL reference clock) / (EXTDIV*2 + 1)
0
PREDIV [5:4]
Pre Divider for HCLK
PREDIV value should be one of 0,1,2,3
Output frequency of PREDIVIDER should be less than 266MHz
0
HALFHCLK [3]
HCLKx1_2(SSMC) clock divider ratio, 0 = HCLK, 1 = HCLK/2
User also has to configure SSMC’s special register which related
with half clock.
1
PCLKDIV [2]
PCLK clock divider ratio, 0 = HCLK, 1 = HCLK / 2
1
HCLKDIV [1:0]
HCLK clock divider ratio
HCLKDIV value should be one of 0,1,3. (2'b10 is invalid)
0x0
ARMCLK Ratio = (ARMDIV+1).
HCLK Ratio = (PREDIV+1) * (HCLKDIV + 1)
Restrictions about changing ARMDIV register.
1. Be careful that ARMCLK should be equal or faster than HCLK. (X times, X is integer)
2. Change PREDIV, HCLKDIV field after 12 HCLK periods as soon as nRESET is released.
Basically, Changing ARMDIV and HCLKDIV simultaneously is supported. When modifying ARMDIV, PREDIV and
HCLKDIV, User should pay attention to obey upper No 1 restriction.