User's Manual

SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR
2-26
The CLKSRC selects the source input of the clocks.
CLKSRC Bit Description Initial Value
RESERVED [31:21] - 0x0_0000
SEL_CAMCLK [20]
Source clock of CAMCLK divider
0 = EPLL, 1 = HCLK
0
SELHSSPI1 [19]
HS-SPI0 clock
0 = EPLL (divided), 1 = MPLL (divided)
0
SELHSSPI0 [18]
HS-SPI0 clock
0 = EPLL (divided), 1 = MPLL (divided)
0
SELHSMMC1 [17]
HSMMC1 clock
0 = EPLL (divided), 1 = EXTCLK
0
SELHSMMC0 [16]
HSMMC0 clock
0 = EPLL (divided), 1 = EXTCLK
0
SELI2S [15:14]
I2S clock source selection
00 = divided clock of EPLL, 01 = external I2S clock
1X = EpllRefClk
0x0
SELI2S_1 [13:12]
I2S_1 clock source selection
00 = divided clock of EPLL, 01 = external I2S clock
1X = EpllRefClk
0x0
RESERVED [11:9] - 0
SELESRC [8:7]
Selection EPLL reference clock
10 = XTAL, 11 = EXTCLK
0x = identical to that of MPLL reference clock
Do not configure SELESRC & SELEPLL register simultaneously.
00
SELEPLL [6]
EsysClk selection
0 = EPLL reference clock, 1 = EPLL output
0
RESERVED [5] - 0
SELMPLL [4]
MSYSCLK selection
0 = MPLL reference clock (produced through clock divider)
1 = MPLL output
0
SELEXTCLK [3]
Configure MPLL reference clock divider
0 = don’t use MPLL reference clock divider (means 1/1 divide ratio)
1 = use MPLL reference clock divider (See EXTDIV field of
CLKDIV)
0
RESERVED [2:0] - 0x0