User's Manual

SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR
2-24
EPLLCON Bit Description Initial Value
RESERVED [31:26] - 0x00
EPLLEN_STOP [25] EPLL ON/OFF in STOP mode. 0:OFF, 1:ON 0
ONOFF [24] EPLL ON/OFF. 0:ON, 1:OFF 1
MDIV [23:16] EPLL main divider value 0x20
RESERVED [15:14] - 0x0
PDIV [13:8] EPLL pre-divider value 0x1
RESERVED [7:3] - 0x00
SDIV [2:0] EPLL post-scaler value 0x2
EPLLCON_K Bit Description Initial Value
RESERVED [31:16] - 0
KDIV [15:0] EPLL fractional modulator 0x0000
The output frequencies of EPLL
can be calculated using the following equations:
F
OUT
= ((m+k/2
16
)× FIN) / (p × 2
s
) (should be 20~600MHz)
Fvco = (m x F
IN
) / p
where, m = MDIV, p = PDIV, s =SDIV, k = KDIV Fin = 10~40MHz
Don't set the value PDIV[5:0] or MDIV[7:0] to all zeros. (6’b00 0000 / 8’b0000 0000)
NOTE
Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL
value recommendation table. If you have to use other values, please contact us.
FIN
(MHz)
FOUT
(MHz)
MDIV
(decimal)
PDIV
(decimal)
SDIV
(decimal)
KDIV
(decimal)
Error [MHz]
12 36 48 1 4 0 0
12 48 32 1 3 0 0
12 60 40 1 3 0 0
12 72 48 1 3 0 0
12 84 28 1 2 0 0
12 96 32 1 2 0 0