User's Manual

S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER
2-23
MPLLCON Bit Description Initial Value
RESERVED [31:26] - 0x00
MPLLEN_STOP [25] MPLL ON/OFF in STOP mode. 0:OFF, 1:ON 0
ONOFF [24] MPLL ON/OFF. 0:ON, 1:OFF 1
MDIV [23:14] Main divider value of MPLL 0x215
RESERVED [13:11] - 0x0
PDIV [10:5] Pre-divider value of MPLL 0x6
RESERVED [4:3] - 0x0
SDIV [2:0] Post-divider value of MPLL 0x0
The output frequencies of MPLL
can be calculated using the following equations:
F
OUT
= (m x F
IN
) / (p x 2
S
) (should be 40~1600MHz)
Fvco = (m x F
IN
) / p (should be 800~1600MHz)
where, m = MDIV, p = PDIV, s = SDIV, Fin = 10~30Mhz
Don't set the value PDIV[5:0] or MDIV[9:0] to all zeros. (6’b00 0000 / 10’b00 0000 0000)
NOTE
Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL
value recommendation table. If you have to use other values, please contact us.
FIN
(MHz)
Target FOUT
(MHz)
MDIV
(decimal)
PDIV
(decimal)
SDIV
(decimal)
Duty
12 240 320 4 2 40~60%
12 400 400 3 2 40~60%
12 450 225 3 1 40~60%
12 500 250 3 1 40~60%
12 534 267 3 1 40~60%
12 600 300 3 1 40~60%
12 800 400 3 1 40~60%