User's Manual

SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR
2-22
8 INDIVIDUAL REGISTER DESCRIPTIONS
8.1 CLOCK SOURCE CONTROL REGISTERS
(LOCKCON0, LOCKCON1, OSCSET, MPLLCON, AND EPLLCON)
The six registers control two internal PLLs and an external oscillator. The output frequency of the PLL is
determined by the divider values of MPLLCON and EPLLCON. The stabilization time for PLLs and the oscillator is
controlled by LOCKCON0/1 and OSCSET, respectively.
Register Address R/W Description Reset Value
LOCKCON0 0x4C00_0000 R/W MPLL lock time count register 0x0000_FFFF
LOCKCON1 0x4C00_0004 R/W EPLL lock time count register 0x0000_FFFF
OSCSET 0x4C00_0008 R/W Oscillator stabilization control register 0x0000_8000
MPLLCON 0x4C00_0010 R/W MPLL configuration register 0x0185_40C0
EPLLCON 0x4C00_0018 R/W EPLL configuration register 0x0120_0102
EPLLCON_K 0x4C00_001C R/W EPLL configuration register for K value 0x0000_0000
Conventional PLL requires stabilization duration after the PLL is ON. The duration can be varied according to the
device variation. Thus, software must adjust these fields with appropriate values in the LOCKCON0/1 register
whose values mean the number of the external reference clock.
LOCKCON0 Bit Description Initial Value
RESERVED [31:16] RESERVED 0x0000
M_LTIME [15:0]
MPLL lock time count value for ARMCLK, HCLK, and PCLK
Typically, M_LTIME must be longer than 300 usec.
0xFFFF
LOCKCON1 Bit Description Initial Value
RESERVED [31:16] RESERVED 0x0000
E_LTIME [15:0]
EPLL lock time count value for UARTCLK, SPICLK and etc.
Typically, E_LTIME must be longer than 300 usec.
0xFFFF
In general, an oscillator requires stabilization time. This register specifies the duration based on the reference
clock.
OSCSET Bit Description Initial Value
RESERVED [31:0] RESERVED 0x0000
XTALWAIT [15:0]
Crystal oscillator settle-down wait time, this value is valid
when s3c2450 is wakeup by stop mode
0x8000