User's Manual

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Table Of Contents

S3C2450 User's Manual
About this Document
- Important Notice
- Notification of Revisions
Table of Contents
- List of Figures
- List of Tables
01-Overview
- 1 INTRODUCTION
- 2 FEATURES
- 3 BLOCK DIAGRAM
- 4 PIN ASSIGNMENTS
02-SYSCON
- 1 OVERVIEW
- 2 FEATURE
- 3 BLOCK DIAGRAM
- 4 FUNCTIONAL DESCRIPTIONS
- 5 CLOCK MANAGEMENT
- 6 POWER MANAGEMENT
- 7 REGISTER DESCRIPTIONS
  - 7.1 ADDRESS MAP
- 8 INDIVIDUAL REGISTER DESCRIPTIONS
03-MATRIX & EBI
- 1 OVERVIEW
- 2 SPECIAL FUNCTION REGISTERS
04-Bus Priority
- 1 OVERVIEW
  - 1.1 BUS PRIORITY MAP
05-SMC
- 1 OVERVIEW
- 2 FEATURE
- 3 BLOCK DIAGRAM
- 4 SPECIAL REGISTERS
06-DRAMC
- 1 OVERVIEW
- 2 BLOCK DIAGRAM
- 3 MOBILE DRAM INITIALIZATION SEQUENCE
07-Nand Flash
- 1 OVERVIEW
- 2 FEATURES
- 3 BLOCK DIAGRAM
- 4 BOOT LOADER FUNCTION
- 5 GPC5/6/7 PIN CONFIGURATION TABLE IN IROM BOOT MODE
- 6 NAND FLASH MEMORY TIMING
- 7 NAND FLASH ACCESS
- 8 DATA REGISTER CONFIGURATION
- 9 STEPPINGSTONE (8KB IN 64KB SRAM)
- 10 1BIT / 4BIT / 8BIT ECC (ERROR CORRECTION CODE)
- 11 MEMORY MAPPING(NAND BOOT AND OTHER BOOT)
- 12 NAND FLASH MEMORY CONFIGURATION
- 13 NAND FLASH CONTROLLER SPECIAL REGISTERS
08-CF controller
- 1 OVERVIEW
- 2 INDIVIDUAL REGISTER DESCRIPTIONS
09-DMA controller
- 1 OVERVIEW
- 2 DMA REQUEST SOURCES
- 3 DMA OPERATION
  - 3.1 EXTERNAL DMA DREQ/DACK PROTOCOL
  - 3.2 EXAMPLES OF POSSIBLE CASES
- 4 DMA SPECIAL REGISTERS
10-Interrupt controller
- 1 OVERVIEW
- 2 INTERRUPT CONTROLLER SPECIAL REGISTERS
11-IOport
- 1 OVERVIEW
- 2 PORT CONTROL DESCRIPTIONS
- 3 I/O PORT CONTROL REGISTER
- 4 GPIO ALIVE & SLEEP PART
12-Watchdog
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 WATCHDOG TIMER OPERATION
- 3 WATCHDOG TIMER SPECIAL REGISTERS
13-PWM Timer
- 1 OVERVIEW
  - 1.1 FEATURE
- 2 PWM TIMER OPERATION
- 3 PWM TIMER CONTROL REGISTERS
14-RTC
- 1 OVERVIEW
15-UART
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 BLOCK DIAGRAM
  - 2.1 UART OPERATION
- 3 UART SPECIAL REGISTERS
16-USB HOST Controller
- 1 OVERVIEW
  - 1.1 USB HOST CONTROLLER SPECIAL REGISTERS
17-USB 2.0 Device
- 1 OVERVIEW
  - 1.1 FEATURE
- 2 BLOCK DIAGRAM
- 3 TO ACTIVATE USB PORT1 FOR USB 2.0 FUNCTION
- 4 SIE (SERIAL INTERFACE ENGINE)
- 5 UPH (UNIVERSAL PROTOCOL HANDLER)
- 6 UTMI (USB 2.0 TRANSCEIVER MACROCELL INTERFACE)
- 7 USB 2.0 FUNCTION CONTROLLER SPECIAL REGISTERS
- 8 REGISTERS
18-IIC bus interface
- 1 OVERVIEW
- 2 IIC-BUS INTERFACE SPECIAL REGISTERS
19-2D
- 1 INTRODUCTION
  - 1.1 FEATURES
- 2 COLOR FORMAT CONVERSION
- 3 COMMAND FIFO
- 4 RENDERING PIPELINE
- 5 REGISTER DESCRIPTIONS
20-HSSPI
- 1 OVERVIEW
- 2 FEATURES
- 3 SIGNAL DESCRIPTIONS
- 4 OPERATION
- 5 SPECIAL FUNCTION REGISTER DESCRIPTIONS
  - 5.1 SETTING SEQUENCE OF SPECIAL FUNCTION REGISTER
  - 5.2 SPECIAL FUNCTION REGISTER
21-HSMMC
- 1 OVERVIEW
- 2 FEATURES
- 3 BLOCK DIAGRAM
- 4 SEQUENCE
- 5 SDI SPECIAL REGISTERS
22-LCD controller
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 FUNCTIONAL DESCRIPTION
- 3 WINDOW BLENDING
  - 3.1 OVERVIEW
  - 3.2 BLENDING DIAGRAM/DETAILS
- 4 VTIME CONTROLLER OPERATION
  - 4.1 RGB INTERFACE
  - 4.2 i80-SYSTEM INTERFACE
- 5 VIRTUAL DISPLAY
- 6 RGB INTERFACE I/O
- 7 LCD CPU INTERFACE I/O (i80-SYSTEM I/F)
- 8 PROGRAMMER’S MODEL
  - 8.1 OVERVIEW
23-Camera Interface
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 EXTERNAL INTERFACE
  - 2.1 SIGNAL DESCRIPTION
  - 2.2 TIMING DIAGRAM
- 3 EXTERNAL/INTERNAL CONNECTION GUIDE
- 4 CAMERA INTERFACE OPERATION
- 5 SOFTWARE INTERFACE
- 6 CAMERA INTERFACE SPECIAL REGISTERS
24-TSADC
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 ADC & TOUCH SCREEN INTERFACE OPERATION
  - 2.1 BLOCK DIAGRAM
  - 2.2 FUNCTION DESCRIPTIONS
- 3 ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS
25-IIS Interface
- 1 OVERVIEW
- 2 FEATURE
- 3 SIGNALS
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTIONS
  - 5.1 MASTER/SLAVE MODE
- 6 AUDIO SERIAL DATA FORMAT
- 7 PROGRAMMING GUIDE
- 8 IIS-BUS INTERFACE SPECIAL REGISTERS
26-IIS Multi Audio Interface
- 1 OVERVIEW
- 2 FEATURE
- 3 SIGNALS
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTIONS
  - 5.1 MASTER/SLAVE MODE
  - 5.2 DMA TRANSFER
- 6 AUDIO SERIAL DATA FORMAT
- 7 PROGRAMMING GUIDE
- 8 IIS-BUS INTERFACE SPECIAL REGISTERS
27-AC97 Controller
- 1 OVERVIEW
  - 1.1 FEATURE
  - 1.2 SIGNALS
- 2 AC97 CONTROLLER OPERATION
  - 2.1 BLOCK DIAGRAM
  - 2.2 INTERNAL DATA PATH
- 3 OPERATION FLOW CHART
- 4 AC-LINK DIGITAL INTERFACE PROTOCOL
  - 4.1 AC-LINK OUTPUT FRAME (SDATA_OUT)
  - 4.2 AC-LINK INPUT FRAME (SDATA_IN)
- 5 AC97 POWER-DOWN
- 6 CODEC RESET
- 7 AC97 CONTROLLER STATE DIAGRAM
- 8 AC97 CONTROLLER SPECIAL REGISTERS
28-PCM Audio Interface
- 1 OVERVIEW
  - 1.1 FEATURE
  - 1.2 SIGNALS
- 2 PCM AUDIO INTERFACE
- 3 PCM TIMING
29-ELECTRICAL DATA
- 1 ABSOLUTE MAXIMUM RATINGS
- 2 RECOMMENDED OPERATING CONDITIONS
- 3 D.C. ELECTRICAL CHARACTERISTICS
- 4 A.C. ELECTRICAL CHARACTERISTICS
30-MECHANICAL DATA
- 1 PACKAGE DIMENSIONS

SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR

2-10

5.6 ARM & BUS CLOCK DIVIDE RATIO

The MSysClk is the base clock for S3C2450 system clock, such as ARMCLK, HCLK, PCLK, DDRCLK, etc.

The Table 2-5 shows the clock division ratios between ARMCLK, HLCK and PCLK. This ratio is determined by

ARMDIV, PREDIV, HCLKDIV and PCLKDIV bits of CLKDIV0 control register.

ARMCLK has to faster or equal with HCLK and synchronous. The Table 2-5 shows that DDRCLK, PCLK,

ARMCLK divide ratio with regard HCLK ratio.

The fraction in the cell is ratio to MSysClk and the value in the round bracket means maximum frequency value.

Table 2-5. Clock Division Ratio of MPLL Region

MSysClk

(800MHz)

HCLK

(133MHz)

DDRCLK

(266MHz)

PCLK, SSMC

(133MHz)

ARMCLK (533MHz)

1/1 1/1 1/1 or 1/2 1/1

1/2 1/1 1/2 or 1/4 1/1 or 1/2

1/3 1/1 1/3 or 1/6 1/1 or 1/3

1/4 1/2 1/4 or 1/8 1/1 or 1/2 or 1/4

1/6 1/3 1/6 or 1/12 1/1 or 1/2 or 1/3 or 1/6

1/8 1/4 1/8 or 1/16 1/1 or 1/2 or 1/4 or 1/8

1/12 1/6 1/12 or 1/24 1/1 or 1/2 or 1/3 or 1/4 or 1/6

1/16 1/8 1/16 or 1/32 1/1 or 1/2 or 1/4 or 1/8