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Table Of Contents

S3C2450 User's Manual
About this Document
- Important Notice
- Notification of Revisions
Table of Contents
- List of Figures
- List of Tables
01-Overview
- 1 INTRODUCTION
- 2 FEATURES
- 3 BLOCK DIAGRAM
- 4 PIN ASSIGNMENTS
02-SYSCON
- 1 OVERVIEW
- 2 FEATURE
- 3 BLOCK DIAGRAM
- 4 FUNCTIONAL DESCRIPTIONS
- 5 CLOCK MANAGEMENT
- 6 POWER MANAGEMENT
- 7 REGISTER DESCRIPTIONS
  - 7.1 ADDRESS MAP
- 8 INDIVIDUAL REGISTER DESCRIPTIONS
03-MATRIX & EBI
- 1 OVERVIEW
- 2 SPECIAL FUNCTION REGISTERS
04-Bus Priority
- 1 OVERVIEW
  - 1.1 BUS PRIORITY MAP
05-SMC
- 1 OVERVIEW
- 2 FEATURE
- 3 BLOCK DIAGRAM
- 4 SPECIAL REGISTERS
06-DRAMC
- 1 OVERVIEW
- 2 BLOCK DIAGRAM
- 3 MOBILE DRAM INITIALIZATION SEQUENCE
07-Nand Flash
- 1 OVERVIEW
- 2 FEATURES
- 3 BLOCK DIAGRAM
- 4 BOOT LOADER FUNCTION
- 5 GPC5/6/7 PIN CONFIGURATION TABLE IN IROM BOOT MODE
- 6 NAND FLASH MEMORY TIMING
- 7 NAND FLASH ACCESS
- 8 DATA REGISTER CONFIGURATION
- 9 STEPPINGSTONE (8KB IN 64KB SRAM)
- 10 1BIT / 4BIT / 8BIT ECC (ERROR CORRECTION CODE)
- 11 MEMORY MAPPING(NAND BOOT AND OTHER BOOT)
- 12 NAND FLASH MEMORY CONFIGURATION
- 13 NAND FLASH CONTROLLER SPECIAL REGISTERS
08-CF controller
- 1 OVERVIEW
- 2 INDIVIDUAL REGISTER DESCRIPTIONS
09-DMA controller
- 1 OVERVIEW
- 2 DMA REQUEST SOURCES
- 3 DMA OPERATION
  - 3.1 EXTERNAL DMA DREQ/DACK PROTOCOL
  - 3.2 EXAMPLES OF POSSIBLE CASES
- 4 DMA SPECIAL REGISTERS
10-Interrupt controller
- 1 OVERVIEW
- 2 INTERRUPT CONTROLLER SPECIAL REGISTERS
11-IOport
- 1 OVERVIEW
- 2 PORT CONTROL DESCRIPTIONS
- 3 I/O PORT CONTROL REGISTER
- 4 GPIO ALIVE & SLEEP PART
12-Watchdog
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 WATCHDOG TIMER OPERATION
- 3 WATCHDOG TIMER SPECIAL REGISTERS
13-PWM Timer
- 1 OVERVIEW
  - 1.1 FEATURE
- 2 PWM TIMER OPERATION
- 3 PWM TIMER CONTROL REGISTERS
14-RTC
- 1 OVERVIEW
15-UART
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 BLOCK DIAGRAM
  - 2.1 UART OPERATION
- 3 UART SPECIAL REGISTERS
16-USB HOST Controller
- 1 OVERVIEW
  - 1.1 USB HOST CONTROLLER SPECIAL REGISTERS
17-USB 2.0 Device
- 1 OVERVIEW
  - 1.1 FEATURE
- 2 BLOCK DIAGRAM
- 3 TO ACTIVATE USB PORT1 FOR USB 2.0 FUNCTION
- 4 SIE (SERIAL INTERFACE ENGINE)
- 5 UPH (UNIVERSAL PROTOCOL HANDLER)
- 6 UTMI (USB 2.0 TRANSCEIVER MACROCELL INTERFACE)
- 7 USB 2.0 FUNCTION CONTROLLER SPECIAL REGISTERS
- 8 REGISTERS
18-IIC bus interface
- 1 OVERVIEW
- 2 IIC-BUS INTERFACE SPECIAL REGISTERS
19-2D
- 1 INTRODUCTION
  - 1.1 FEATURES
- 2 COLOR FORMAT CONVERSION
- 3 COMMAND FIFO
- 4 RENDERING PIPELINE
- 5 REGISTER DESCRIPTIONS
20-HSSPI
- 1 OVERVIEW
- 2 FEATURES
- 3 SIGNAL DESCRIPTIONS
- 4 OPERATION
- 5 SPECIAL FUNCTION REGISTER DESCRIPTIONS
  - 5.1 SETTING SEQUENCE OF SPECIAL FUNCTION REGISTER
  - 5.2 SPECIAL FUNCTION REGISTER
21-HSMMC
- 1 OVERVIEW
- 2 FEATURES
- 3 BLOCK DIAGRAM
- 4 SEQUENCE
- 5 SDI SPECIAL REGISTERS
22-LCD controller
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 FUNCTIONAL DESCRIPTION
- 3 WINDOW BLENDING
  - 3.1 OVERVIEW
  - 3.2 BLENDING DIAGRAM/DETAILS
- 4 VTIME CONTROLLER OPERATION
  - 4.1 RGB INTERFACE
  - 4.2 i80-SYSTEM INTERFACE
- 5 VIRTUAL DISPLAY
- 6 RGB INTERFACE I/O
- 7 LCD CPU INTERFACE I/O (i80-SYSTEM I/F)
- 8 PROGRAMMER’S MODEL
  - 8.1 OVERVIEW
23-Camera Interface
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 EXTERNAL INTERFACE
  - 2.1 SIGNAL DESCRIPTION
  - 2.2 TIMING DIAGRAM
- 3 EXTERNAL/INTERNAL CONNECTION GUIDE
- 4 CAMERA INTERFACE OPERATION
- 5 SOFTWARE INTERFACE
- 6 CAMERA INTERFACE SPECIAL REGISTERS
24-TSADC
- 1 OVERVIEW
  - 1.1 FEATURES
- 2 ADC & TOUCH SCREEN INTERFACE OPERATION
  - 2.1 BLOCK DIAGRAM
  - 2.2 FUNCTION DESCRIPTIONS
- 3 ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS
25-IIS Interface
- 1 OVERVIEW
- 2 FEATURE
- 3 SIGNALS
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTIONS
  - 5.1 MASTER/SLAVE MODE
- 6 AUDIO SERIAL DATA FORMAT
- 7 PROGRAMMING GUIDE
- 8 IIS-BUS INTERFACE SPECIAL REGISTERS
26-IIS Multi Audio Interface
- 1 OVERVIEW
- 2 FEATURE
- 3 SIGNALS
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTIONS
  - 5.1 MASTER/SLAVE MODE
  - 5.2 DMA TRANSFER
- 6 AUDIO SERIAL DATA FORMAT
- 7 PROGRAMMING GUIDE
- 8 IIS-BUS INTERFACE SPECIAL REGISTERS
27-AC97 Controller
- 1 OVERVIEW
  - 1.1 FEATURE
  - 1.2 SIGNALS
- 2 AC97 CONTROLLER OPERATION
  - 2.1 BLOCK DIAGRAM
  - 2.2 INTERNAL DATA PATH
- 3 OPERATION FLOW CHART
- 4 AC-LINK DIGITAL INTERFACE PROTOCOL
  - 4.1 AC-LINK OUTPUT FRAME (SDATA_OUT)
  - 4.2 AC-LINK INPUT FRAME (SDATA_IN)
- 5 AC97 POWER-DOWN
- 6 CODEC RESET
- 7 AC97 CONTROLLER STATE DIAGRAM
- 8 AC97 CONTROLLER SPECIAL REGISTERS
28-PCM Audio Interface
- 1 OVERVIEW
  - 1.1 FEATURE
  - 1.2 SIGNALS
- 2 PCM AUDIO INTERFACE
- 3 PCM TIMING
29-ELECTRICAL DATA
- 1 ABSOLUTE MAXIMUM RATINGS
- 2 RECOMMENDED OPERATING CONDITIONS
- 3 D.C. ELECTRICAL CHARACTERISTICS
- 4 A.C. ELECTRICAL CHARACTERISTICS
30-MECHANICAL DATA
- 1 PACKAGE DIMENSIONS

USER'S MANUAL

S3C2450

16/32-Bit RISC Microprocessor

August 2008

REV 1.11

Confidential Proprietary of Samsung Electronics Co., Ltd

Summary of content (820 pages)

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Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
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NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea PRODUCT NAME: S3C2450 RISC Microprocessor DOCUMENT NAME: S3C2450 User's Manual, Revision 1.11 DOCUMENT NUMBER: 21.10-S3-C2450-082008 EFFECTIVE DATE: August, 2008 DIRECTIONS: Revision 1.11 REVISION HISTORY Revision No Description of Change Refer to Author(s) Date 0.00 S3C2450X User’s Manual Preliminary Revision 0.0 release - AP app part. February 27, 2008 0.
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REVISION DESCRIPTIONS FOR REVISION 1.11 Chapter Chapter Name Page Subjects (Major changes comparing with last version) 1. Overview 1-3 UART part is updated. 2. System controller 2-13 Entering into IDLE mode is changed. 2. System controller 2-14 Entering into IDLE mode is changed. 2. System controller 2-20 Entering into IDLE mode is changed. 2. System controller 2-31 Entering into IDLE mode is changed. 15. UART 15-11 UART Clock and PCLK relation is updated. 23.
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Table of Contents Chapter 1 Product Overview 1 Introduction ............................................................................................................................................... 1-1 2 Features .................................................................................................................................................... 1-2 3 Block Diagram...........................................................................................................................
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Table of Contents (Continued) Chapter 2 System Controller (Continued) 8 Individual Register Descriptions................................................................................................................2-22 8.1 Clock Source Control Registers (LOCKCON0, LOCKCON1, OSCSET, MPLLCON, and EPLLCON) ..............................................2-22 8.2 Clock Control Register (CLKSRC, CLKDIV, HCLKCON, PCLKCON, and SCLKCON).................2-25 8.3 Power Management Registers (PWRMODE and PWRCFG) ....
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Table of Contents (Continued) Chapter 5 Static Memory Controller (SMC) 1 Overview ................................................................................................................................................... 5-1 2 Feature...................................................................................................................................................... 5-2 3 Block Diagram.................................................................................................
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Table of Contents (Continued) Chapter 7 NAND Flash Controller 1 Overview....................................................................................................................................................7-1 2 Features ....................................................................................................................................................7-1 3 Block Diagram ...........................................................................................................
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Table of Contents (Continued) Chapter 8 CF Controller 1 Overview ................................................................................................................................................... 8-1 1.1 Features........................................................................................................................................... 8-1 1.2 Signal description ..................................................................................................................
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Table of Contents (Continued) Chapter 9 DMA Controller 1 Overview....................................................................................................................................................9-1 2 DMA Request Sources..............................................................................................................................9-2 3 DMA Operation...............................................................................................................................
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Table of Contents (Continued) Chapter 11 I/O Ports 1 Overview ................................................................................................................................................... 11-1 2 Port Control Descriptions .......................................................................................................................... 11-9 2.1 Port Configuration Register (GPACON-GPMCON) ........................................................................ 11-9 2.
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Table of Contents (Continued) Chapter 12 WatchDog Timer 1 Overview....................................................................................................................................................12-1 1.1 Features...........................................................................................................................................12-1 2 Watchdog Timer Operation ............................................................................................................
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Table of Contents (Continued) Chapter 14 Real Time Clock (RTC) 1 Overview ................................................................................................................................................... 14-1 1.1 Features........................................................................................................................................... 14-1 1.2 Real Time Clock Operation Description ....................................................................................
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Table of Contents (Continued) Chapter 17 USB 2.0 Function 1 Overview....................................................................................................................................................17-1 1.1 Feature.............................................................................................................................................17-1 2 Block Diagram ....................................................................................................................
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Table of Contents (Continued) Chapter 18 IIC-Bus Interface 1 Overview ................................................................................................................................................... 18-1 1.1 IIC-Bus Interface.............................................................................................................................. 18-3 1.2 Start And Stop Conditions ........................................................................................................
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Table of Contents (Continued) Chapter 20 HS_SPI Controller 1 Overview....................................................................................................................................................20-1 2 Features ....................................................................................................................................................20-1 3 Signal Descriptions.......................................................................................................
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Table of Contents (Continued) Chapter 21 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 5.30 5.31 5.32 5.33 5.34 5.35 SD/MMC Host Controller (Continued) Block Gap Control Register........................................................................................................... 21-38 Wakeup Control Register .............................................................................................................. 21-40 Clock Control Register ...............
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Table of Contents (Continued) Chapter 23 Camera Interface 1 Overview....................................................................................................................................................23-1 1.1 Features...........................................................................................................................................23-2 2 External Interface ................................................................................................................
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Table of Contents (Continued) Chapter 23 6.31 6.32 6.33 6.34 6.35 6.36 6.37 6.38 6.39 6.40 6.41 6.42 6.43 6.44 6.45 6.46 6.47 6.48 6.49 6.50 6.51 Camera Interface (Continued) Preview Pre-Scaler Control Register 1 ......................................................................................... 23-35 Preview Pre-Scaler Control Register 2 ......................................................................................... 23-35 Preview Main-Scaler Control Register ..............................
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Table of Contents (Continued) Chapter 25 IIS-Bus Interface 1 Overview....................................................................................................................................................25-1 2 Feature ......................................................................................................................................................25-1 3 Signals..................................................................................................................
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Table of Contents (Continued) Chapter 26 IIS Multi Audio Interface (Continued) 7 Programming Guide.................................................................................................................................. 26-8 7.1 Initialization ...................................................................................................................................... 26-8 7.2 Play Mode (TX mode) with DMA ....................................................................................
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Table of Contents (Continued) Chapter 28 PCM Audio Interface 1 Overview....................................................................................................................................................28-1 1.1 Feature.............................................................................................................................................28-1 1.2 Signals .....................................................................................................................
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List of Figures Figure Number Title Page Number 1-1 1-2 1-3 S3C2450 Block Diagram ............................................................................................. 1-5 S3C2450 Pin Assignments (400-FBGA) Top view...................................................... 1-6 Memory Map ................................................................................................................ 1-32 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 System Controller Block Diagram........
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List of Figures Figure Number Title Page Number 7-1 7-2 7-3 7-4 7-5 7-6 7-7 NAND Flash Controller Block Diagram........................................................................7-2 NAND Flash Controller Boot Loader Block Diagram ...................................................7-2 CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) Block Diagram ................7-3 nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram .................................7-4 NAND Flash Memory Mapping Block Diagram.........
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List of Figures Figure Number Title Page Number 14-1 14-2 14-3 Real Time Clock Block Diagram.................................................................................. 14-2 RTC Tick Interrupt Clock Scheme ............................................................................... 14-5 Main Oscillator Circuit Example................................................................................... 14-6 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 UART Block Diagram (with FIFO) ..................
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List of Figures Figure Number Title Page Number 20-1 HS_SPI Transfer Format..............................................................................................20-4 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 21-14 21-15 21-16 HSMMC Block Diagram ...............................................................................................21-2 SD Card Detect Sequence...........................................................................................
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List of Figures Figure Number 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 23-10 23-11 23-12 23-13 23-14 Title Page Number 23-15 23-17 23-18 23-19 23-20 23-21 23-22 23-23 Camera interface overview .......................................................................................... 23-1 ITU-R BT 601 Input Timing Diagram ........................................................................... 23-3 ITU-R BT 601 Interlace Timing Diagram ..............................................................
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List of Figures Figure Number Title Page Number 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-9 AC97 Block Diagram....................................................................................................27-2 Internal Data Path ........................................................................................................27-3 AC97 Operation Flow Chart.........................................................................................
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List of Figures Figure Number 30-1 30-2 Title Page Number 400-FBGA-1313 Package Dimension 1 (Top View).................................................... 30-1 400-FBGA-1313 Package Dimension 2 (Bottom View)...............................................
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List of Tables Table Number Title Page Number 1-1 1-1 1-1 1-1 1-2 1-3 1-4 1-5 1-6 1-7 400-Pin FBGA Pin Assignments − Pin Number Order (1/4) ........................................1-7 400-Pin FBGA Pin Assignments − Pin Number Order (2/4) ........................................1-8 400-Pin FBGA Pin Assignments − Pin Number Order (3/4) ........................................1-9 400-Pin FBGA Pin Assignments – Pin Number Order (4/4) ........................................
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List of Tables Table Number Title Page Number 17-1 17-2 Non-Indexed Registers ................................................................................................ 17-5 Indexed Registers........................................................................................................ 17-6 20-1 External Signals Description........................................................................................ 20-2 21-1 21-2 21-3 21-4 21-5 21-6 Determination of Transfer Type..........
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List of Tables Table Number 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 29-12 29-13 29-14 29-15 29-16 29-17 29-18 29-19 29-20 29-21 29-22 xxx Title Page Number Absolute Maximum Rating ...........................................................................................29-1 Recommended Operating Conditions (400MHz).........................................................29-2 Recommended Operating Conditions (533MHz).........................................................
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List of Tables Table Number Title Page Number 17-1 17-2 Non-Indexed Registers ................................................................................................17-5 Indexed Registers ........................................................................................................17-6 20-1 External Signals Description ........................................................................................20-2 21-1 21-2 21-3 21-4 21-5 21-6 Determination of Transfer Type ..........
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List of Tables Table Number Title Page Number 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 29-12 29-13 29-14 29-15 29-16 29-17 29-18 29-19 29-20 29-21 29-22 Absolute Maximum Rating........................................................................................... 29-1 Recommended Operating Conditions (400MHz) ........................................................ 29-2 Recommended Operating Conditions (533MHz) ........................................................
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S3C2450X RISC MICROPROCESSOR 1 PRODUCT OVERVIEW PRODUCT OVERVIEW 1 INTRODUCTION This user’s manual describes SAMSUNG's S3C2450 16/32-bit RISC microprocessor. SAMSUNG’s S3C2450 is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2450 includes the following components. The S3C2450 is developed with ARM926EJ core, 65nm CMOS standard cells and a memory complier.
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR 2 FEATURES 2.1.1 Architecture 2.1.3 NAND Flash • Integrated system for hand-held devices and general embedded applications. • • 16/32-Bit RISC architecture and powerful instruction set with ARM926EJ CPU core. Supports booting from NAND flash memory by selecting OM as IROM boot mode. (Only 8bit Nand and 8ECC is supported when it boots) • Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux.
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW 2 FEATURES (Continued) 2.1.6 Interrupt Controller 2.1.11 LCD Controller • • Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color • Supports 16, 24 bpp non-palette true-color displays for color • Supports maximum 16M color at 24 bpp mode • Supports multiple screen size – Typical actual screen size: 640x480, 320x240, 160x160, and others. – Maximum frame buffer size is 4Mbytes.
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PRODUCT OVERVIEW 2 S3C2450X RISC MICROPROCESSOR FEATURES (Continued) 2.1.14 A/D Converter & Touch Screen Interface • 10-ch multiplexed ADC • Max. 500KSPS and 12-bit Resolution • Internal FET for direct Touch screen interface 2.1.15 Watchdog Timer • Master mode only, this block always sources the main shift clock • Input (16bit 32depth) and output(16bit 32depth) FIFOs to buffer data 2.1.21 USB Host • • 2-port USB Host 16-bit Watchdog Timer • • Complies with OHCI Rev. 1.
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW 3 BLOCK DIAGRAM Figure 1-1.
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4 PIN ASSIGNMENTS A B C D E F G H J K L M N P R T U V W Y AA AB AC Bottom View Figure 1-2.
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1.
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR Table 1-1.
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-1.
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR Table 1-1.
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-2.
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 35 RDATA2 RDATA2 - Hi-z pvhbsudtbrt 36 RDATA1 RDATA1 - Hi-z pvhbsudtbrt 37 RDATA0 RDATA0 - Hi-z pvhbsudtbrt 38 CAMVSYNC/GPJ9 GPJ9 -/- I pvhbsudtart 39 CAMHREF/GPJ10 GPJ10 -/- I pvhbsudtart 40 VSSi VSSi - P vddivh_alv 41 VDDi VDDi - P vssipvh_alv 42 CAMPCLK/GPJ8 GPJ8 -/- I pvhbsudtart 43 CAMDATA0/GPJ0 GPJ0 -/- I pvhbsudtart
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 71 VSS_LCD VSS_LCD - P vsstvh_alv 72 VDD_LCD VDD_LCD - P vddtvh_alv 73 RGB_VD2/GPC10 GPC10 -/- I pvhbsudtart 74 RGB_VD3/GPC11 GPC11 -/- I pvhbsudtart 75 RGB_VD4/GPC12 GPC12 -/- I pvhbsudtart 76 RGB_VD5/GPC13 GPC13 -/- I pvhbsudtart 77 RGB_VD6/GPC14 GPC14 -/- I pvhbsudtart 78 RGB_VD7/GPC15 GPC15 -/- I pvhbsudtart 79 RGB_VD8/GPD
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 107 VSSiarm VSSiarm - P vssicvlh_alv 108 TCLK/GPB4 GPB4 -/- I pvhbsudtart 109 nXBACK/GPB5 GPB5 -/- I pvhbsudtart 110 nXBREQ/GPB6/RTCK RTCK -/- I pvhbsudtart 111 VDD_OP2 VDD_OP2 - P vddtvh_alv 112 VSS_OP2 VSS_OP2 - P vsstvh_alv 113 nXDACK1/GPB7/I2C_SDA1 GPB7 -/- I pvhbsudtart 114 nXDREQ1/GPB8/I2C_SCL1 GPB8 -/- I pvhbsudtart 115
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 143 VSSiarm VSSiarm - P vssicvlh_alv 144 IICSCL/GPE14 GPE14 -/- I pvhbsudtart 145 IICSDA/GPE15 I2SLRCK/GPE0/ AC_nRESET/PCM0_FSYNC GPE15 -/- I pvhbsudtart -/-/- I -/-/- I -/-/- I -/-/- I -/-/- I 146 147 148 I2SSCLK/GPE1/AC_SYNC/ PCM0_SCLK I2SCDCLK/GPE2/ AC_BIT_CLK0/PCM0_CDCLK GPE0 GPE1 GPE2 pvhbsudtart pvhbsudtart pvhbsudtart 149 I2SSDI/GPE3/A
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 175 SD1_DAT[1]/GPL1 GPL1 -/- I pvhbsudtart 176 SD1_DAT[2]/GPL2 GPL2 -/- I pvhbsudtart 177 SD1_DAT[3]/GPL3 GPL3 -/- I pvhbsudtart 178 SD1_DAT[4]/GPL4/I2S1_ SCLK/PCM1_SCLK GPL4 -/- I 179 SD1_DAT[5]/GPL5/I2S1_ CDCLK/PCM1_CDCLK GPL5 -/- I 180 SD1_DAT[6]/GPL6/I2S1_ SDI/PCM1_SDI GPL6 -/- I 181 SD1_DAT[7]/GPL7/I2S1_ SDO/PCM1_SDO GPL7 -/- I 182
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 208 VDDA_ADC VDDA_ADC - P vddtvh_alv 209 VDD_RTC VDD_RTC - P vddrtcvh_alv 210 Xtortc Xtortc - AO pvhsosca 211 Xtirtc Xtirtc - AI pvhsosca 212 OM[4] OM[4] - I pvhbsudtart_alv 213 OM[3] OM[3] - I pvhbsudtart_alv 214 OM[2] OM[2] - I pvhbsudtart_alv 215 OM[1] OM[1] - I pvhbsudtart_alv 216 OM[0] OM[0] - I pvhbsudtart_alv 217
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 244 EINT10/GPG2 GPG2 -/- I pvhbsudtart_alv 245 EINT11/GPG3 GPG3 -/- I pvhbsudtart_alv 246 EINT12/GPG4 GPG4 -/-/- I pvhbsudtart_alv 247 EINT13/GPG5 GPG5 -/- I pvhbsudtart_alv 248 EINT14/GPG6 GPG6 -/- I pvhbsudtart_alv 249 EINT15/GPG7 GPG7 -/- I pvhbsudtart_alv 250 VDD_OP1 VDD_OP1 - P vddtvh_alv 251 DP DP - AI usb6002x1_t 252 DN
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 280 VDDi VDDi - P vddivh_alv 281 VSSi VSSi - P vssipvh_alv 282 SDATA25/GPK9 SDATA25 - Hi-z pvmbsudtbrt 283 SDATA24/GPK8 SDATA24 - Hi-z pvmbsudtbrt 284 SDATA23/GPK7 SDATA23 - Hi-z pvmbsudtbrt 285 SDATA22/GPK6 SDATA22 - Hi-z pvmbsudtbrt 286 SDATA21/GPK5 SDATA21 - Hi-z pvmbsudtbrt 287 VDD_SDRAM VDD_SDRAM - P vddtvm_alv 288 VSS_SD
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 316 VDD_SDRAM VDD_SDRAM - P vddtvm_alv 317 VSS_SDRAM VSS_SDRAM - P vsstvm_alv 318 DQS1 DQS1 O(L) Hi-z pvmbsudtbrt 319 DQS0 DQS0 O(L) Hi-z pvmbsudtbrt 320 DQM3/GPA26 DQM3 O(H)- O(L) pvmbsudtbrt 321 DQM2/GPA25 DQM2 O(H) O(L) pvmbsudtbrt 322 DQM1 DQM1 O(H) O(L) pvmbsudtbrt 323 DQM0 DQM0 O(H) O(L) pvmbsudtbrt 324 nSCS[0] nSCS[0]
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 352 SADDR12 SADDR12 - O(L) pvmbsudtbrt 353 VDD_SDRAM VDD_SDRAM - P vddtvm_alv 354 VSS_SDRAM VSS_SDRAM - P vsstvm_alv 355 SADDR13 SADDR13 - O(L) pvmbsudtbrt 356 SADDR14 SADDR14 - O(L) pvmbsudtbrt 357 SADDR15 SADDR15 - O(L) pvmbsudtbrt 358 VDDi VDDi - P vddivh_alv 359 VSSi VSSi - P vssipvh_alv 360 nWE_CF/GPA27 nWE_CF -/- O(H)
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR Pin Number Pin Name Default Function I/O State @Sleep I/O State @nRESET I/O Type 387 VDD_SRAM VDD_SRAM - P vddtvh_alv 388 VSS_SRAM VSS_SRAM - P vsstvh_alv 389 RADDR4 RADDR4 - O(L) pvhbsudtbrt 390 RADDR3 RADDR3 - O(L) pvhbsudtbrt 391 RADDR2 RADDR2 - O(L) pvhbsudtbrt 392 RADDR1 RADDR1 - O(L) pvhbsudtbrt 393 RADDR0/GPA0 RADDR0 -/- O(L) pvhbsudtbrt 394 nRBE1 nRBE1 - O(H) pvhbsudtbrt 395 nRBE0 nRBE0 - O(H)
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-3. I/O Cell Types and Descriptions Cell Name Ftn. Interface Voltage CMOS /Schmitt Retention IO Pull-up /Control Pull-down /Control Driver Strength Pvhbdc Bi 1.8/2.5/3.3V analog - - - - Pvhbr Bi 1.8/2.5/3.3V analog - - - - pvhbsudtart Bi 1.8/2.5/3.3V Schmit Y Y Y 2.6/5.2/7.8/10.5mA pvhbsudtart_alv Bi 1.8/2.5/3.3V Schmit N Y Y 2.6/5.2/7.8/10.5mA pvhbsudtbrt Bi 1.8/2.5/3.3V Schmit Y Y Y 3.3/6.6/9.9/13.
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PRODUCT OVERVIEW 4.1 S3C2450X RISC MICROPROCESSOR SIGNAL DESCRIPTIONS Table 1-4. S3C2450 Signal Descriptions Signal In/Out Description Reset, Clock & Power XTIpll AI Crystal input signals for internal osc circuit. When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK source. If it isn't used, it has to be Low (0V) XTOpll AO Crystal output signals for internal osc circuit. When OM[0] = 0, XTIpll is used for MPLL CLK source and EPLL CLK source.
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S3C2450X RISC MICROPROCESSOR Signal PRODUCT OVERVIEW In/Out Description nRBE[1:0] O Upper byte/lower byte enable (In case of 16-bit SRAM) nWAIT I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current bus cycle cannot be completed. If nWAIT signal isn’t used in your system, nWAIT signal must be tied on pull-up resistor.
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PRODUCT OVERVIEW Signal RGB_VCLK/SYS_WR S3C2450X RISC MICROPROCESSOR In/Out O Description RGB I/F LCD Clock i80 I/F Write Enable RGB_VSYNC/SYS_CS1 O RGB I/F Vertical Sync. Signal i80 I/F Sub LCD Select RGB_HSYNC/SYS_CS0 O RGB I/F Horizontal Sync.
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S3C2450X RISC MICROPROCESSOR Signal Vref PRODUCT OVERVIEW In/Out Description AI ADC reference voltage IICSDA IO IIC-bus data IICSCL IO IIC-bus clock IICSDA1 IO IIC-bus data IICSCL1 IO IIC-bus clock I2SLRCK IO IIS-bus channel select clock I2SSCLK IO IIS-bus serial clock I2SCDCLK IO CODEC system clock IIC-Bus IIS-Multi Audio Interface I2SSDI I IIS-bus serial data input I2SSDO O IIS-bus serial data output(Front Left, Right) I2SSDO_1 O IIS-bus serial data output(Front Cente
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PRODUCT OVERVIEW Signal S3C2450X RISC MICROPROCESSOR In/Out Description DN IO DATA(–) from USB host. (Need to 15kΩ pull-down) DP IO DATA(+) from USB host. (Need to 15kΩ pull-down) DM_UDEV IO DATA(–) for USB peripheral. DP_UDEV IO DATA(+) for USB peripheral. REXT O External Resistor ( 44.2ohm +/- 1%) USB Device XO_UDEV OSC Crystal output XI_UDEV OSC Crystal input SPI SPIMISO[1:0] IO SPIMISO is the master data input line, when SPI is configured as a master.
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S3C2450X RISC MICROPROCESSOR Signal PRODUCT OVERVIEW In/Out Description TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic. TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and data. TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and data. RTCK O Returned Clock VDDalive P S3C2450 reset block and port status register VDD. It should be always supplied whether in normal mode or in Sleep mode.
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PRODUCT OVERVIEW Signal S3C2450X RISC MICROPROCESSOR In/Out Description VDDA33C/VDDA33T1 P USB 2.0 PHY Power ( 3.3V) VSSA33C/VSSA33T2 G USB 2.0 PHY Ground NOTE: I/O : Input/Output. AI/AO : Analog I/O. ST : Schmitt-trigger. P : Power. G : Ground.
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S3C2450X RISC MICROPROCESSOR 4.2 PRODUCT OVERVIEW S3C2450 OPERATION MODE DESCRIPTION Table 1-5.
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PRODUCT OVERVIEW 4.3 S3C2450X RISC MICROPROCESSOR S3C2450 MEMORY MAP AND BASE ADDRESS OF SPECIAL REGISTERS 4.3.
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Table 1-6.
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR Table 1-7. S3C2450 Special Registers Register Name Acc.
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S3C2450X RISC MICROPROCESSOR Register Name PRODUCT OVERVIEW Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Acc.
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S3C2450X RISC MICROPROCESSOR Register Name PRODUCT OVERVIEW Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Address Reset Value Acc.
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S3C2450X RISC MICROPROCESSOR Register Name Address PRODUCT OVERVIEW Reset Value Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Address Reset Value Acc.
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S3C2450X RISC MICROPROCESSOR Register Name PRODUCT OVERVIEW Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Acc.
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S3C2450X RISC MICROPROCESSOR Register Name PRODUCT OVERVIEW Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Address Reset Value Acc.
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S3C2450X RISC MICROPROCESSOR Register Name Address PRODUCT OVERVIEW Reset Value Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Acc.
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S3C2450X RISC MICROPROCESSOR Register Name PRODUCT OVERVIEW Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Acc.
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S3C2450X RISC MICROPROCESSOR Register Name PRODUCT OVERVIEW Address Reset Value GPJSEL 0x560000dc 0x0 GPKCON 0x560000E0 GPKDAT 0x560000E4 0x0 GPKUDP 0x560000E8 GPLCON Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Acc.
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S3C2450X RISC MICROPROCESSOR Register Name PRODUCT OVERVIEW Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Acc.
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Address Reset Value Acc.
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PRODUCT OVERVIEW Register Name S3C2450X RISC MICROPROCESSOR Acc.
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S3C2450X RISC MICROPROCESSOR Register Name PRODUCT OVERVIEW Acc. Read/ Unit Write Address Reset Value CW_RB_X_REG 0x4D408234 0x0000_0000 R/W Right X coordinate of Clip Window. CW_RB_Y_REG 0x4D408238 0x0000_0000 R/W Bottom Y coordinate of Clip Window. COORD0_REG 0x4D408300 0x0000_0000 R/W Coordinates 0 register. COORD0_X_REG 0x4D408304 0x0000_0000 R/W X coordinate of Coordinates 0. COORD0_Y_REG 0x4D408308 0x0000_0000 R/W Y coordinate of Coordinates 0.
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PRODUCT OVERVIEW Register Name DEST_BASE_ADDR_REG 1-56 S3C2450X RISC MICROPROCESSOR Address Reset Value 0x4D408734 0x0000_0000 Acc.
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S3C2450X RISC MICROPROCESSOR PRODUCT OVERVIEW Cautions on S3C2450 Special Registers 1. 2. 3. 4. S3C2450 does not support the big endian mode. The special registers have to be accessed for each recommended access unit. All registers except ADC registers, RTC registers and UART registers must be read/write in word unit (32-bit). Make sure that the ADC registers, RTC registers and UART registers be read/write by the specified access unit and the specified address. 5.
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PRODUCT OVERVIEW S3C2450X RISC MICROPROCESSOR NOTES 1-58
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S3C2450X RISC MICROPROCESSOR 2 SYSTEM CONTROLLER SYSTEM CONTROLLER 1 OVERVIEW The system controller consists of three parts; reset control, system clock control, and system power-management control. The system clock control logic in S3C2450 can generate the required system clock signals which are the inputs of ARM926EJ, several AHB blocks, and APB blocks. There are two PLLs in S3C2450 to generate internal clocks. One is for general functional blocks, which include ARM, AHB, and APB.
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR 3 BLOCK DIAGRAM off-part alive-part Glue Clocks Glue Clock Generator Power Management AHB Register Signal Masking Power Management Reset Control Reset Power ON/OFF Register Figure 2-1. System Controller Block Diagram Figure 2-1 shows the system controller block diagram. The system controller is divided into two blocks, which are the OFF block and the ON block. Since the system controller must be alive when the external power supply is disabled.
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S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER 4 FUNCTIONAL DESCRIPTIONS The system controller for S3C2450 has three functions, which include the reset management, the clock generation, and the power management. In this section, the behavior will be described. 4.1 RESET MANAGEMENT AND TYPES S3C2450 has four types of resets and reset controller in system controller can place the system into the predefined states with one of the following four resets.
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR POWER nRESET EXTCLK or XTIpll PLL is configured by S/W first time Clock disable Lock time VCO is adapte to new clock frequency . VCO output SYSCLK The logic is operarted by EXTCLK or XTIpll SYSCLK is FOUT Figure 2-2. Power-On Reset Sequence 4.3 WATCHDOG RESET Watchdog reset is invoked when software fails to prevent the watchdog timer from timing out.
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S3C2450X RISC MICROPROCESSOR 4.4 SYSTEM CONTROLLER SOFTWARE RESET Software can initialize the device state itself when it writes “0x533C_2450” to SWRST register. During the software reset, the following actions occur : • All units(except some blocks listed in table 2-1 ) go into their pre-defined reset state. • All pins get their reset state, and BATT_FLT pin is ignored. • The nRSTOUT pin is asserted during software reset. Software reset is invoked then, the following sequence occurs. : 1.
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR 5 CLOCK MANAGEMENT 5.1 CLOCK GENERATION OVERVIEW Figure 2-3 shows the block diagram of the clock generation module. The main clock source comes from an external crystal (XTI) or external clock (EXTCLK). EPLL’s input clock is one of the XTI or EXTCLK. Clock selection can be done by configuring MUX selection signal. When both XTI and EXTCLK are running, GFM(Glitch Free Mux)’s output can be configured easily without generating glitch.
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S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER Table 2-3. Clock Source Selection for the EPLL CLKSRC[8] (register) CLKSRC[7] (register) OM[0] EPLL Reference Clock 0 X 0 XTI 0 X 1 EXTCLK 1 0 X XTI 1 1 X EXTCLK Table 2-4.
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SYSTEM CONTROLLER 5.3 S3C2450X RISC MICROPROCESSOR PLL (PHASE-LOCKED-LOOP) The PLL (Phase-Locked Loop) frequency synthesizer is constructed in CMOS on single monolithic structure. The PLL provides frequency multiplication capabilities. MPLL generates the clock sources for ARMCLK, HCLK, PCLK, DDRCLK and SSMCCLK and EPLL generates clock sources for USBHOSTCLK, CAMCLK and so forth.
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S3C2450X RISC MICROPROCESSOR 5.5 SYSTEM CONTROLLER SYSTEM CLOCK CONTROL The ARMCLK is used for ARM926EJ core, the main CPU of S3C2450. The HCLK is the reference clock for internal AHB bus and peripherals such as the memory controller, the interrupt controller, LCD controller, the DMA, USB host block, System Controller, Power down controller and etc. The PCLK is used for internal APB bus and peripherals such as WDT, IIS, I2C, PWM timer, ADC, UART, GPIO, RTC and SPI etc.
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SYSTEM CONTROLLER 5.6 S3C2450X RISC MICROPROCESSOR ARM & BUS CLOCK DIVIDE RATIO The MSysClk is the base clock for S3C2450 system clock, such as ARMCLK, HCLK, PCLK, DDRCLK, etc. The Table 2-5 shows the clock division ratios between ARMCLK, HLCK and PCLK. This ratio is determined by ARMDIV, PREDIV, HCLKDIV and PCLKDIV bits of CLKDIV0 control register. ARMCLK has to faster or equal with HCLK and synchronous. The Table 2-5 shows that DDRCLK, PCLK, ARMCLK divide ratio with regard HCLK ratio.
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S3C2450X RISC MICROPROCESSOR 5.7 SYSTEM CONTROLLER EXAMPLES FOR CONFIGURING CLOCK REGITER TO PRODUCE SPECIFIC FREQUENCY OF AMBA CLOCKS.
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR Figure 2-9 shows EPLL and special clocks for various peripherals Figure 2-9. EPLL Based Clock Domain 5.8 ESYSCLK CONTROL Clocks of the EPLL can be used for various peripherals. Each divider value is configured in CLKDIV1 register and all clocks are enabled or disabled by accessing SCLKCON register. According to USB host interface, If you want to get the clock with exact 50% duty cycle, then make EPLL generate 96MHz and divide the clock.
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S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER 6 POWER MANAGEMENT The power management block controls the system clocks by software for the reduction of power consumption in S3C2450. These schemes are related to PLL, clock control logic(ARMCLK, HCLK, PCLK) and wake-up signal. S3C2450 has four power-down modes. The following section describes each power management mode. Related registers are PWRMODE, PWRCFG and WKUPSTAT. 6.
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SYSTEM CONTROLLER 6.2 S3C2450X RISC MICROPROCESSOR POWER SAVING MODES S3C2450 can support various power saving modes. These are Normal mode, idle mode, Stop mode, Deep-stop mode and Sleep mode. 6.2.1 Normal Mode (General Clock Gating Mode) In General Clock Gating mode, the On/Off clock gating of the individual clock source of each IP block is performed by controlling of each corresponding clock source enable bit. The Clock Gating is applied instantly whenever the corresponding bit (or bits) is changed.
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S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER 6. System controller request memory controller to enter self refresh mode. It is for preserving contents in SDRAM. 7. System controller wait for self refresh acknowledge from memory controller. 8. After receiving the self-refresh acknowledge, system controller disables system clocks, and switches SYSCLK’s source to MPLL reference clock. 9. Disables PLLs and Crystal(XTI) oscillation.
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR 6.2.4 SLEEP MODE In the SLEEP Mode, all the clock sources are off and also the internal logic-power is not supplied except for the wake-up logic circuitry. In this mode, the static power-dissipation of internal logic can be minimized. SLEEP Mode Entering sequence is as follows. 1. User writes command into the system controller’s PWRMODE[15:0] register to let system enter into the SLEEP Mode. 2.
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S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER a Figure 2-11.
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR SLEEP mode is initiated Wake-up event ARM Down Req. & Ack. ARMCLK BUS Down Req. & Ack. DRAM Self Refresh Req. & Ack. CKE (DRAM) SYSCLK PWR_EN Figure 2-12.
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S3C2450X RISC MICROPROCESSOR 6.3 SYSTEM CONTROLLER WAKE-UP EVENT When S3C2450 wakes up from the STOP Mode by an External Interrupt, a RTC alarm interrupt and other interrupts, the PLL is turned on automatically. The initial-state of S3C2450 after wake-up from the SLEEP Mode is almost the same as the Power-On-Reset state except for the contents of the external DRAM is preserved. In contrast, S3C2450 automatically recovers the previous working state after wake-up from the STOP Mode.
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SYSTEM CONTROLLER 6.5 S3C2450X RISC MICROPROCESSOR POWER SAVING MODE ENTERING/EXITING CONDITION Table 2-8 shows that Power Saving mode state and Entering or Exiting condition. In general, the entering conditions are set by the main CPU. Pleas refer to power-related registers(PWRMODE, PWRCFG and WKUPSTAT) before adopting power saving scheme on your system. In dealing with sleep mode, It is good for you to know following two restrictions.
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S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER 7 REGISTER DESCRIPTIONS The system controller registers are divided into seven categories; clock source control, clock control, power management, reset control, system controller status, bus configuration, and misc. The following section will describe the behavior of the system controller. 7.1 ADDRESS MAP Table 2-9 summarizes the address map of the system controller. Table 2-9.
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SYSTEM CONTROLLER 8 S3C2450X RISC MICROPROCESSOR INDIVIDUAL REGISTER DESCRIPTIONS 8.1 CLOCK SOURCE CONTROL REGISTERS (LOCKCON0, LOCKCON1, OSCSET, MPLLCON, AND EPLLCON) The six registers control two internal PLLs and an external oscillator. The output frequency of the PLL is determined by the divider values of MPLLCON and EPLLCON. The stabilization time for PLLs and the oscillator is controlled by LOCKCON0/1 and OSCSET, respectively.
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S3C2450X RISC MICROPROCESSOR MPLLCON RESERVED SYSTEM CONTROLLER Bit [31:26] Description Initial Value - 0x00 MPLLEN_STOP [25] MPLL ON/OFF in STOP mode. 0:OFF, 1:ON 0 ONOFF [24] MPLL ON/OFF.
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SYSTEM CONTROLLER EPLLCON RESERVED S3C2450X RISC MICROPROCESSOR Bit [31:26] Description Initial Value - 0x00 EPLLEN_STOP [25] EPLL ON/OFF in STOP mode. 0:OFF, 1:ON 0 ONOFF [24] EPLL ON/OFF.
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S3C2450X RISC MICROPROCESSOR 8.2 SYSTEM CONTROLLER CLOCK CONTROL REGISTER (CLKSRC, CLKDIV, HCLKCON, PCLKCON, AND SCLKCON) The clock generator within the system controller has many dividers and MUXs to generate appropriate clocks. These clocks are controlled by the clock control registers as described in here.
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR The CLKSRC selects the source input of the clocks.
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S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER The CLKDIV0 configures the division ratio of each clock generator. The operating speed of ARM can be slow to reduce the overall power dissipation, if software doest not require full operating performance. In this case, the power dissipation due to the ARM core can be reduced if the DVS field is ON. The set of DVS field makes that the operating frequency of ARM is the same as system operating clock (HCLK).
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR CLKDIV1 configures the clock ratio related on EPLL. CLKDIV1 Bit Description Initial Value RESERVED [31:30] - 0 CAMDIV [29:26] CAM clock divider ratio.
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S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER The AHB and APB clocks are en/disabled by HCLKCON register. All reserved bits have 1 value at initial state.
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR The special clocks are controlled by SCLKCON register. Some blocks in the device require several operating frequencies, i.e., 48 MHz and 24 MHz for USB interface block. Thus, these output frequencies can be controlled by the CLKDIV values.
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S3C2450X RISC MICROPROCESSOR 8.3 SYSTEM CONTROLLER POWER MANAGEMENT REGISTERS (PWRMODE AND PWRCFG) If you want to change the power management mode, you just write a bit(s) into PWRMODE register. Before writing, you must configure condition to wake-up from the power down mode.
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SYSTEM CONTROLLER PWRCFG S3C2450X RISC MICROPROCESSOR Bit Description RTC_CFG [8] Configure RTC alarm interrupt wakeup mask 0 = Wake-up signal event is generated when RTC alarm occurs. 1 = Mask RTC alarm interrupt RTCTICK_CFG [7] Configure RTC Tick interrupt wakeup mask 0 = wake-up signal event is generated when RTC Tick occurs. 1 = mask RTC alarm interrupt RESERVED [6:5] Initial Value 0 0 These bits must be 0b’00 0 0 nSW_PHY_ OFF_USB [4] Power on/off of USB PHY.
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S3C2450X RISC MICROPROCESSOR 8.4 SYSTEM CONTROLLER RESET CONTROL REGISTERS (SWRST AND RSTCON) Software can reset S3C2450 using SWRST register. The waveform of the reset signals are determined by RSTCON register.
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SYSTEM CONTROLLER 8.5 S3C2450X RISC MICROPROCESSOR CONTROL OF RETENTION PAD(I/O) WHEN NORMAL MODE AND WAKE-UP FROM SLEEP MODE. Figure 2-13. Usage of PWROFF_SLP S3C2450 has a lot of retention PADs. Retention pad’s ability is remaining data when internal logic power is off. In normal mode, PWROFF_SLP signal which from RSTCON register can control about PAD output. If SLP_IN signal has LOW value, data assigned to specific PAD go out through level shifter and latch.
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S3C2450X RISC MICROPROCESSOR 8.6 SYSTEM CONTROLLER SYSTEM CONTROLLER STATUS REGISTERS (WKUPSTAT AND RSTSTAT) Software must know the status of the system controller after wakeup or reset. WKUPSTAT and RSTSTAT registers store the information.
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SYSTEM CONTROLLER 8.7 S3C2450X RISC MICROPROCESSOR BUS CONFIGURATION REGISTER (BUSPRI0, BUSPRI1, AND BUSMISC) To improve AHB bus performance, software must control the arbitration scheme and type. Register Address R/W Description Reset Value BUSPRI0 0x4C00_0050 R/W Bus priority control register 0 0x0000_0000 S3C2450 consists of 2 hierarchical AHB buses. The arbitration priority and order can be configured with BUSPRI0 registers.
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S3C2450X RISC MICROPROCESSOR BUSPRI0 SYSTEM CONTROLLER Bit Initial Value Description Fixed priority order for AHB-I bus [2:0] ORDER_I 8.
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SYSTEM CONTROLLER 8.9 S3C2450X RISC MICROPROCESSOR USB PHY CONTROL REGISTER (PHYCTRL) Register Address R/W Description Reset Value PHYCTRL 0x4C00_0080 R/W USB2.0 PHY Control Register 0x0000_0000 PHYCTRL RESERVED CLK_ON_OFF Bit [31:6] [5] Description Initial State - 0 Clock input on off control at pad input area Should be use with EXT_CLK [2]. When Combination of [5],[2] bit is 2’b11 , could be off clock input.
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S3C2450X RISC MICROPROCESSOR SYSTEM CONTROLLER 8.10 USB PHY POWER CONTROL REGISTER (PHYPWR) Register Address R/W PHYPWR 0x4C00_0084 R/W PHYCTRL Description USB2.0 PHY Power Control Register Bit Description Reset Value 0x0000_0000 Initial State RESERVED [31:6] Must be zero 0 RESERVED [5:4] Must be 0x3 2’b00 RESERVED [3:1] Must be zero 2’b000 FORCE_ SUSPEND [0] Apply Suspend signal for power save 0 = Disable (Normal Operation) 1 = Enable 0 8.
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SYSTEM CONTROLLER S3C2450X RISC MICROPROCESSOR 8.12 USB CLOCK CONTROL REGISTER (UCLKCON) Register Address R/W UCLKCON 0x4C00_008C R/W MSINTEN DETECT_VBUS RESERVED Bit [31] [30:3] Description USB Clock Control Register Description Reset Value 0x0000_0000 Initial State VBUS Detect This VBUS indicator signal indicates that the VBUS signal on the USB cable is active. For the serial interface, this signal controls the pull-up resistance on the D+ line in Device mode only.
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S3C2450X RISC MICROPROCESSOR 3 BUS MATRIX & EBI BUS MATRIX & EBI 1 OVERVIEW S3C2450 MATRIX provides the interface between dual AHB bus and Memory sub-system. It is used for achieving high system performance by accessing various kinds of memory (SDRAM, SRAM, Flash Memory, ROM etc) from different AHB bus (one is for system and the other is for image) at the same time.
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BUS MATRIX & EBI S3C2450X RISC MICROPROCESSOR 2 SPECIAL FUNCTION REGISTERS 2.1 MATRIX CORE 0 PRIORITY REGISTER (BPRIORITY0) Register Address R/W BPRIORITY0 0X4E800000 R/W BPRIORITY0 Description Matrix Core 0 priority control register Bit PRI_TYP [2] Description Reset Value 0x0000_0004 Initial State Priority type 1 0 = Fixed Type 1 = Rotation Type FIX_PRI_TYP [0] Priority for the fixed priority type 0 0 = AHB_S > AHB_I 1 = AHB_I > AHB_S 2.
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S3C2450X RISC MICROPROCESSOR 2.
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BUS MATRIX & EBI S3C2450X RISC MICROPROCESSOR NOTES 3-4
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S3C2450X RISC MICROPROCESSOR 4 BUS PRIORITIES BUS PRIORITIES 1 OVERVIEW The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode and fixed priority mode. 1.1 BUS PRIORITY MAP The S3C2450 holds 16 masters on the AHB_S(System Bus), 9 masters on the AHB_I(Image Bus) and 9masters on the APB Bus. The following list shows the priorities among these bus masters after a reset.
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BUS PRIORITIES 4-2 S3C2450X RISC MICROPROCESSOR Priority AHB_I BUS MASTERS 0 Reserved 1 TFTW1-LCD 2 TFTW2-LCD 3 CAMIF_PREVIEW 4 CAMIF_CODEC 5 CAMIF_PIP 6 2D 7 AHB2AHB 8 Default Priority APB BUS MASTERS 0 AHB2APB 1 DMA0 2 DMA1 3 DMA2 4 DMA3 5 DMA4 6 DMA5 7 DMA6 8 DMA7 Comment 1. Fix Type: all priority can be changed according to register value stored in The System Controller.
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S3C2450X RISC MICROPROCESSOR 5 STATIC MEMORY CONTROLLER STATIC MEMORY CONTROLLER (SMC) 1 OVERVIEW The SMC provides simultaneous support for up to six memory banks (bank0 to bank5) that you can configure independently. Each memory bank supports: • SRAM • ROM • Flash EPROM • Burst SRAM, ROM, and flash • OneNAND You can configure each memory bank to use 8 or 16-bit external memory data paths. You can configure the SMC to support either little-endian or big-endian operation.
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STATIC MEMORY CONTROLLER S3C2450X RISC MICROPROCESSOR 2 FEATURE • Supports asynchronous static memory-mapped devices including RAM, ROM, OneNAND and flash • Supports synchronous static memory-mapped devices including synchronous burst flash • Supports asynchronous page mode read operation in non-clocked memory subsystems • Supports asynchronous burst mode read access to burst mode ROM and flash devices • Supports synchronous burst mode read, write access to burst mode ROM and flash devices • Su
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S3C2450X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER 3 BLOCK DIAGRAM SMC SMC Core Memory Control Signals AHB Slave Interface Pad Interface AHB Slave Interface Data and Address Bus Data bus TIC Interface Figure 5-1.
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STATIC MEMORY CONTROLLER 3.1 S3C2450X RISC MICROPROCESSOR ASYNCHRONOUS READ Figure 5-3 shows an external memory read transfer with two output enable delay states, WSTOEN = 2, and two wait states, WSTRD = 2. Four AHB wait states are inserted during the transfer, two for the standard read, and additional two because of the programmed wait states added. The PSMAVD signal might be required for synchronous static memory devieces when you use it in asynchronous mode.
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S3C2450X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER SMCLK ADDR A nCS nOE nWAIT DATA ( R ) D(A) Figure 5-5.
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STATIC MEMORY CONTROLLER 3.2 S3C2450X RISC MICROPROCESSOR ASYNCHRONOUS BURST READ The SMC supports sequential access asynchronous burst reads to four or eight consecutive locations in 8 or 16bit memories, as set using the BurstLenRead bits of the Control Register SMBCRx. Burst mode is enabled by setting the Burst Mode bits, BMRead or BMWrite, in the Control register.
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S3C2450X RISC MICROPROCESSOR 3.3 STATIC MEMORY CONTROLLER SYNCHRONOUS READ/SYNCHRONOUS BURST READ Single synchronous read operations have the same control signal timing as an asynchronous read operation, but with different timing requirements for setup and hold relative to the clock. Because the output signals of the SMC are generated internally from clocked logic, the timing for single synchronous reads is the same as for asynchronous reads.
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STATIC MEMORY CONTROLLER 3.4 S3C2450X RISC MICROPROCESSOR ASYNCHRONOUS WRITE You can program the delay between the assertion of the chip select and the write enable from 0-15 cycles using the WSTWEN bits of the Bank Write Enable Assertion Delay Control Register, SMBWSTWENRx. This reduces the power consumption for memories. The write enable is asserted on the rising edge of nSMMEMCLK, half a clock after the assertion of chip select.
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S3C2450X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER SMCLK ADDR A nCS nWE nWAIT DATA ( W ) D(A) Figure 5-9. Write Timing Diagram (DRnCS = 1, DRnOWE = 0) SMCLK ADDR A nCS nWE nWAIT DATA ( W ) D(A) Figure 5-10.
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STATIC MEMORY CONTROLLER 3.5 S3C2450X RISC MICROPROCESSOR SYNCHRONOUS WRITE/ SYNCHRONOUS BURST WRITE Figure 5-11 shows an example synchronous write operation. In this example the signal SMADDRVALID provides a one-cycle pulse. This behavior is enabled by setting the SyncWriteDev bit in the SMBCRx register. You must also set the AddrValidWriteEn bit for synchronous write. The signal PnWE is only active for one cycle.
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S3C2450X RISC MICROPROCESSOR 3.6 STATIC MEMORY CONTROLLER BUS TURNAROUND You can configure the SMC for each memory bank to use external bus turnaround cycles between read and write memory accesses. You can program the IDCY field for up to 15 bus turnaround wait states. This avoids bus contention on the external memory data bus.
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STATIC MEMORY CONTROLLER 3.6.
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S3C2450X RISC MICROPROCESSOR STATIC MEMORY CONTROLLER 3.6.2 SRAM Memory Interface Examples Figure 5-13. Memory Interface with 8-bit SRAM (2MB) Figure 5-14. Memory Interface with 16-bit SRAM (4MB) Addr.
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STATIC MEMORY CONTROLLER S3C2450X RISC MICROPROCESSOR 4 SPECIAL REGISTERS 4.
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S3C2450X RISC MICROPROCESSOR 4.
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STATIC MEMORY CONTROLLER 4.
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S3C2450X RISC MICROPROCESSOR 4.
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STATIC MEMORY CONTROLLER Bit BurstLen Read [11:10] SyncReadDev [9] BMRead [8] DRnCS [7] SMBLSPOL [6] MW [5:4] Reserved [3] WaitEn [2] WaitPol [1] RBLE [0] S3C2450X RISC MICROPROCESSOR Description Initial State Burst transfer length. Sets the number of sequential transfers that the burst device supports for a read: 00 = 4-transfer burst. 01 = 8-transfer burst. 10 = 16-transfer burst. 11 = Reserved Synchronous access capable device connected.
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S3C2450X RISC MICROPROCESSOR 4.7 STATIC MEMORY CONTROLLER BANK ONENAND TYPE SELECTION REGISTER Register Address R/W SMBONETYPER 0x4F000100 R/W Description SMC Bank OneNAND type selection register Bit [31:6] BANK5TYPE [5] Description Reset Value 0x0 Initial State Read undefined.
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STATIC MEMORY CONTROLLER 4.9 S3C2450X RISC MICROPROCESSOR SMC CONTROL REGISTER Register Address R/W SMCCR 0x4F000204 R/W Description SMC control register Bit [31:2] MemClkRatio [1] Description Reset Value 0x3 Initial State Read undefined. Write as zero. 0x0 Defines the ratio of SMCLK to HCLK: 0x1 0 = SMCLK = HCLK. 1 = SMCLK = HCLK/2. SMClockEn [0] SMCLK enable: 0 = Clock only active during memory accesses. 1 = Clock always running.
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S3C2450X RISC MICROPROCESSOR 6 MOBILE DRAM CONTROLLER MOBILE DRAM CONTROLLER 1 OVERVIEW The S3C2450 Mobile DRAM Controller supports three kinds of memory interface - (Mobile) SDRAM and mobile DDR and DDR2. Mobile DRAM controller provides 2 chip select signals (2 memory banks), these are used for up to 2 (mobile) SDRAM banks or 2 mobile DDR banks or 2 DDR2 banks.
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MOBILE DRAM CONTROLLER S3C2450X RISC MICROPROCESSOR 2 BLOCK DIAGRAM Follow Figure 6-1 shows the block diagram of Mobile DRAM Controller Figure 6-1.
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S3C2450X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER 3 MOBILE DRAM INITIALIZATION SEQUENCE On power-on reset, software must initialize the memory controller and the mobile DRAM connected to the controller. Refer to the mobile DRAM(SDRAM or mDDR or DDR2) data sheet for the start up procedure, and example sequences are given below: 3.1 MOBILE DRAM(SDRAM OR MOBILE DDR) INITIALIZATION SEQUENCE 1. Wait 200us to allow DRAM power and clock stabilize. 2. Setting the Configuration Register0.
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MOBILE DRAM CONTROLLER S3C2450X RISC MICROPROCESSOR 3.2.1 (Mobile) SDRAM Memory Interface Examples A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A14 A15 DQM0 DQM1 BA0 BA1 LDQM UDQM SCKE SCLK SCKE SCLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRASn SCASn WE Figure 6-2.
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S3C2450X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER 3.2.2 Mobile DDR (and DDR2) Memory Interface Examples A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A14 A15 DQM0 DQM1 DQS0 DQS1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 LDQM UDQM DQS0 DQS1 SCKE SCLK SCLKn CKE CK nCK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 nSCS nSRAS nSCAS nWE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nSCS0 nSRASn SCASn WE Figure 6-4.
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MOBILE DRAM CONTROLLER S3C2450X RISC MICROPROCESSOR 3.2.3 Supported Programmable Timing Parameters Figure 6-5. DRAM Timing Diagram Figure 6-5 shows a timing diagram of DRAM. There are many timing parameters provided by DRAM. And DRAMC only provides some timing parameters to support various DRAM memories, like SDR, mobile DDR and DDR2. tARFC and tRP are programmable, so you can also control the tRAS period by using these parameters. And the delay from RAS to CAS is determined by tRCD.
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S3C2450X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER DRAMC also needs tARFC timing parameter to control of the timing for auto-refresh to CMD and self-refresh to CMD period. The Figure 6-7 shows the tARFC timing diagram. Figure 6-7.
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MOBILE DRAM CONTROLLER 3.
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S3C2450X RISC MICROPROCESSOR 3.
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MOBILE DRAM CONTROLLER 3.
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S3C2450X RISC MICROPROCESSOR 3.6 MOBILE DRAM CONTROLLER MOBILE DRAM (EXTENDED ) MODE REGISTER SET REGISTER Register Address R/W BANKCON3 0x4800000C R/W Description Mobile DRAM (E)MRS Register Reset Value 0x8000_0003 3.6.
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MOBILE DRAM CONTROLLER S3C2450X RISC MICROPROCESSOR 3.6.2 DDR2 Memory MRS[15:0] and EMRS(1)[31:16] PnBANKCON BA Bit [31:30] Description Initial State Bank address for EMRS 10b Reserved [29] Should be ‘0’ 0b Qoff [28] 0 = Output buffer enable 1 = Output buffer disable 0b RDQS [27] 0 = Disable 1 = Enable 0b nDQS [26] 0 = Enable 1 = Disable 0b OCD program [25:23] Refer to DDR2 spec. 000b Additive latency [21:19] Refer to DDR2 spec.
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S3C2450X RISC MICROPROCESSOR MOBILE DRAM CONTROLLER 3.6.3 DDR2 Memory EMRS(2)[31:16] PnBANKCON Bit Description BA [31:30] Bank address for EMRS Reserved [29:24] Should be ‘0’ Initial State 10b 000000b High Temperature Self-Refresh Rate Enable SRF Reserved [23] [22:20] DCC [19] PASR [18:16] 0b 0 = Disable 1 = Enable Should be ‘0’ 000b 0 = Disable 1 = Enable 0b PASR(Partial Array Self Refresh) for EMRS(2) 000b 3.6.
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MOBILE DRAM CONTROLLER 3.7 S3C2450X RISC MICROPROCESSOR MOBILE DRAM REFRESH CONTROL REGISTER Register Address R/W REFRESH 0x48000010 R/W REFRESH Reserved Bit Description Mobile DRAM refresh control register Description [31:16] Reserved Reset Value 0x0000_0020 Initial State 0x0000 DRAM refresh cycle. REFCYC 3.8 Example: Refresh period is 15.6us, and HCLK is 66MHz. The value of REFCYC is as follows: REFCYC = 15.
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S3C2450X RISC MICROPROCESSOR 7 NAND FLASH CONTROLLER NAND FLASH CONTROLLER 1 OVERVIEW S3C2450 boot code can be executed on an external NAND flash memory. The S3C2450 is equipped with an internal SRAM buffer called ‘Steppingstone’. This supports NAND flash boot loader. When you use IROM boot and select nand flash as boot device, first 8 KB of the NAND flash memory will be loaded in the Steppingstone by IROM and the boot code will be executed in the steppingstone.
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NAND FLASH CONTROLLER S3C2450X RISC MICROPROCESSOR 3 BLOCK DIAGRAM ECC Gen. NAND FLASH Interface SYSTEM BUS SFR Control & State Machine RnB I/O0 - I/O7 AHB Slave I/F Stepping Stone Controller nFCE CLE ALE nRE nWE Stepping Stone (64KB SRAM) Figure 7-1. NAND Flash Controller Block Diagram 4 BOOT LOADER FUNCTION REGISTERS AUTO BOOT CORE ACCESS (Boot Code) Stepping Stone (64KB Buffer) NAND FLASH Controller USER ACCESS NAND FLASH Memory Special Function Registers Figure 7-2.
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 5 GPC5/6/7 PIN CONFIGURATION TABLE IN IROM BOOT MODE Page Address Cycle GPC7 [2] GPC6 [1] GPC5 [0] MMC(MoviNAND/iNand) - - 0 0 0 Reserved - - 0 0 1 3 0 1 0 4 0 1 1 4 1 0 0 5 1 0 1 5 1 1 0 512 Nand 2048 4096 Above configuration is applicable when NAND Flash is used as booting memory in IROM boot mode. If NAND Flash is not used as boot memory, the configuration can be changed by setting NFCON SFR ’NFCONF’ (0x4E000000).
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NAND FLASH CONTROLLER S3C2450X RISC MICROPROCESSOR TWRPH0 TWRPH1 HCLK nWE / nRE DATA DATA Figure 7-4. nWE & nRE Timing (TWRPH0=0, TWRPH1=0) Block Diagram 7 NAND FLASH ACCESS S3C2450 does not support NAND flash access mechanism directly. It only supports signal control mechanism for NAND flash access. Therefore software is responsible for accessing NAND flash memory correctly. 1. Writing to the command register (NFCMMD) = the NAND Flash Memory command cycle 2.
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 8 DATA REGISTER CONFIGURATION 8.1.1 8-bit NAND Flash Memory Interface A. B. C.
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NAND FLASH CONTROLLER S3C2450X RISC MICROPROCESSOR 10.1.1 1-BIT ECC Register Configuration Following tables shows the configuration of 1-bit ECC value read from spare area of external NAND flash memory. For comparing to ECC parity code generated by the H/W modules, each ECC data read from memory must be written to NFMECCDn for main area and NFSECCD for spare area. NOTE 4-bit ECC decoding scheme is different to 1-bit ECC. 1.
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 10.2 1-BIT ECC PROGRAMMING ENCODING AND DECODING 1. To use 1-bit ECC in software mode, reset the ECCType to ‘0’ (enable 1-bit ECC)‘. ECC module generates ECC parity code for all read / write data when MainECCLock (NFCONT[7]) and SpareECCLock (NFCONT[6]) are unlocked(‘0’).
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NAND FLASH CONTROLLER S3C2450X RISC MICROPROCESSOR 10.4 4-BIT ECC PROGRAMMING GUIDE (DECODING) 1. To use 4-bit ECC, set the MsgLength to 0(512-byte message length) and set the ECCType to ‘1’(enable 4-bit ECC). ECC module generates ECC parity code for 512-byte read data. So, you have to reset ECC value by writing the InitMECC (NFCONT[5]) bit as ‘1’ and have to clear the MainECCLock (NFCONT[7]) bit to ‘0’(Unlock) before read data.
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 4. To generate spare area ECC parity code, set the MsgLength to 1(24-byte message length), and set the ECCType to “01”(enable 8bit ECC). 8bit ECC module generates the ECC parity code for 24-byte data. In order to initiating the module, you have to write ‘1’ on the InitMECC (NFCONT[5]) bit after clearing the MainECCLock (NFCONT[7]) bit to ‘0’(Unlock). MainECCLock (NFCONT[7]) bit controls whether ECC Parity code is generated or not.
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NAND FLASH CONTROLLER S3C2450X RISC MICROPROCESSOR 11 MEMORY MAPPING(NAND BOOT AND OTHER BOOT) 0x40000_0000 SRAM (8KB) SRAM (8KB) SDRAM (nSCS1) SDRAM (nSCS1) MPORT1 0x3800_0000 SDRAM (nSCS0) SDRAM (nSCS0) SROM (nRCS5) SROM (nRCS5) SROM (nRCS4) SROM (nRCS4) SROM (nRCS3) ROM (nRCS3) 0x3000_0000 0x2800_0000 0x2000_0000 0x1800_0000 0x1000_0000 0x0800_0000 0x0000_0000 MPORT0 SROM (nRCS2) SROM (nRCS2) SROM (nRCS1) SROM (nRCS1) SROM (nRCS0) Internal iROM Using OneNAND for boot ROM
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 12 NAND FLASH MEMORY CONFIGURATION Figure 7-6. A 8-bit NAND Flash Memory Interface Block Diagram NOTE: NAND CONTROLLER can support to control two nand flash memories . NAND CS Other BOOT nFCE NAND CONTROLLER CS0 Configurable nRCS[1] NAND CONTROLLER CS1 Configurable If you want NAND BOOT by IROM, nFCE must be used to boot.
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NAND FLASH CONTROLLER S3C2450X RISC MICROPROCESSOR 13 NAND FLASH CONTROLLER SPECIAL REGISTERS 13.
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.2 NAND FLASH CONFIGURATION REGISTER Register Address R/W Description Reset Value NFCONF 0x4E000000 R/W NAND Flash Configuration register 0xX000100X NFCONF Bit Description Initial State Reserved [31] Reserved 0 Reserved [30] Should be 0 0 Reserved [29:26] MsgLength [25] Reserved 0000 Message (Data) length for 4/8 bit ECC 0 0 = 512-byte 1 = 24-byte ECCType [24:23] This bit indicates what kind of ECC should be used.
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NAND FLASH CONTROLLER NFCONF AddrCycle S3C2450X RISC MICROPROCESSOR Bit Description Initial State [1] This bit indicates the number of Address cycle of NAND Flash memory. H/W Set (CfgAddrCycle) When Page Size is 512 Bytes, 0 = 3 address cycle 1 = 4 address cycle When page size is 2K or 4K, 0 = 4 address cycle 1 = 5 address cycle This bit is determined by OM[1] pin on reset and wake-up time from sleep mode. This bit can be changed by software later.
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.
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NAND FLASH CONTROLLER NFCONT EnbIllegalAccINT S3C2450X RISC MICROPROCESSOR Bit [10] Description Illegal access interrupt control Initial State 0 0 = Disable interrupt 1 = Enable interrupt Illegal access interrupt will occurs when CPU tries to program or erase locking area (the area setting in NFSBLK (0x4E000020) to NFEBLK (0x4E000024)).
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.4 COMMAND REGISTER Register Address R/W NFCMMD 0x4E000008 R/W NFCMMD Description NAND Flash command set register Bit Description Reset Value 0x00 Initial State Reserved [31:8] Reserved 0x00 NFCMMD [7:0] NAND Flash memory command value 0x00 13.
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NAND FLASH CONTROLLER S3C2450X RISC MICROPROCESSOR 13.7 MAIN DATA AREA ECC REGISTER Register Address R/W NFMECCD0 0x4E000014 R/W Description NAND Flash ECC 1st 2nd register for main area data read Reset Value 0x00000000 Note: Refer to ECC Module Features. NFMECCD1 0x4E000018 R/W NAND Flash ECC 3rd 4th register for main area data read 0x00000000 Note: Refer to ECC Module Features.
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.9 PROGRMMABLE BLOCK ADDRESS REGISTER Register Address R/W Description Reset Value NFSBLK 0x4E000020 R/W NAND Flash programmable start block address 0x000000 NFEBLK 0x4E000024 R/W NAND Flash programmable end block address 0x000000 Nand Flash can be programmed between start and end address. When the Soft lock or Lock-tight is enabled and the Start and End address has same value, Entire area of NAND flash will be locked.
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NAND FLASH CONTROLLER S3C2450X RISC MICROPROCESSOR The NFSLK and NFEBLK can be changed while Soft lock bit(NFCONT[16]) is enabled. But cannot be changed when Lock-tight bit(NFCONT[17]) is set. NAND flash memory Locked area (Read only) NFEBLK+1 NFEBLK When NFSBLK > NFEBLK Address High Prorammable/ Readable Area NFSBLK NFEBLK NFSBLK Locked area (Read only) Low when Lock-tight =1 or SoftLock=1 Figure 7-7.
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S3C2450X RISC MICROPROCESSOR 13.10 NAND FLASH CONTROLLER NFCON STATUS REGISTER Register Address R/W NFSTAT 0x4E000028 R/W NFSTAT Description NAND Flash operation status register Bit Description Reset Value 0x0080001D Initial State Reserved [31:24] Read undefined 0x00 Reserved [23:7] Reserved 0x00 ECCDecDone [6] When 4-bit ECC or 8-bit ECC decoding is finished, this value set and issue interrupt if enabled. The NFMLCBITPT, NFMLCL0 and NFMLCEL1 have valid values.
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NAND FLASH CONTROLLER 13.11 S3C2450X RISC MICROPROCESSOR ECC0/1 ERROR STATUS REGISTER Register Address R/W Description Reset Value NFECCERR0 0x4E00002C R NAND Flash ECC Error Status register for I/O [7:0] 0xX0XX_XXXX NFECCERR1 0x4E000030 R NAND Flash ECC Error Status register for I/O [7:0] 0x0000_0000 13.11.1 When ECCType is 1-bit ECC.
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S3C2450X RISC MICROPROCESSOR NAND FLASH CONTROLLER 13.11.2 When ECCType is 4-bit ECC.
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NAND FLASH CONTROLLER 13.12 S3C2450X RISC MICROPROCESSOR MAIN DATA AREA ECC0 STATUS REGISTER Register Address R/W Description Reset Value NFMECC0 0x4E000034 R NAND Flash ECC status register 0xXXXXXX NFMECC1 0x4E000038 R NAND Flash ECC status register 0xXXXXXX 13.12.
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S3C2450X RISC MICROPROCESSOR 13.
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NAND FLASH CONTROLLER 13.
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S3C2450X RISC MICROPROCESSOR 13.
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NAND FLASH CONTROLLER 13.
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S3C2450X RISC MICROPROCESSOR 8 CF CONTROLLER CF CONTROLLER 1 OVERVIEW CF controller supports PC card memory/IO mode & True-IDE mode. CF controller is compatible with CF standard spec. R3.0. 1.1 FEATURES 1.1.1 The CF Controller Features: The CF controller supports only 1 slot. The CF controller consists of 2 parts − PC card controller & ATA controller. They are multiplexing from or to PAD signals. Users have to use the only 1 mode, PC card or True-IDE mode. Default mode is PC card mode.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 1.2 SIGNAL DESCRIPTION CF Interface Signals Pins I/O Description nCD_CF 1 I Card detect signals (software control by GPIO MISCCR[30]) nIREQ_CF(EINT[19]) 1 I Interrupt request from CF card. PC card mode: active low (memory mode: level triggering, I/O mode: edge triggering).
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 1.3 BLOCK DIAGRAM 1.3.1 Top-Level Block Diagram A top-level block diagram of the overall CF controller is shown below in Figure 8-1. CF controller AHB master IF CF card AHB slave IF PC card controller IDE mode Output pad enble Card power enable Top level SFR Address decoder AHB Back born ATA controller HADDR Figure 8-1.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 1.3.2 PC Card Controller Block Diagram A top-level block diagram of the PC card controller is shown below in Figure 8-2. PC card controller Block ADDR 11 nWE,nOE nIOWR, nIORD nREG Main Controller WDATA 16 RDATA 16 Special Function Register Data Buffer & Controller Top Controller nCE1, nCE2 nCD Write_dir Address decoder Address & Command buffer 32 32 32 32 nWAIT Figure 8-2.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 1.3.3 ATA Controller Block Diagram A top-level block diagram of the ATA controller is shown below in Figure 8-3. ATA controller Block control/interrupt ATA interface ATA interface Data control CRC AHB Slave interface AHB slave IF ATA write data 16 16 Configuration Register Interrupt source 16 Control/Status Register PIO data ATA read data Transfer control Data control FIFO (32-bit x 16) AHB Master interface AHB master IF Figure 8-3.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 1.4 TIMING DIAGRAM 1.4.1 PC Card Mode nCE1 nCE2 IORD IOWR nOE nWE IDLE SET UP COMMAND HOLD IDLE Figure 8-4.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 1.4.2 True-IDE Mode 1.4.3 PIO Mode PIO Mode Waveform t1 t1 CS0, CS1 DA[2:0] teoc t2 DIOR-/ DIOW- WR DD[15:0] or DD[7:0] RD DD[15:0] or DD[7:0] Figure 8-5. PIO Mode Waveform 1.4.4 Timing Parameter In PIO Mode Table 8-1.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 1.5 SPECIAL FUNCTION REGISTERS 1.5.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 1.5.2 Memory Map Table Table 8-2.
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CF CONTROLLER Register S3C2450X RISC MICROPROCESSOR Address Description Reset Value ATA_PIO_LLR 0x4B801960 ATA PIO device LBA low register 0x00000000 ATA_PIO_LMR 0x4B801964 ATA PIO device LBA middle register 0x00000000 ATA_PIO_LHR 0x4B801968 ATA PIO device LBA high register 0x00000000 ATA_PIO_DVR 0x4B80196C ATA PIO device register 0x00000000 ATA_PIO_CSD 0x4B801970 ATA PIO device command/status register 0x00000000 ATA_PIO_DAD 0x4B801974 ATA PIO device control/alternate status regi
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 2 INDIVIDUAL REGISTER DESCRIPTIONS 2.1 MUX_REG REGISTER Register Address R/W Description Reset Value MUX_REG 0x4B801800 R/W MUX_REG is used to set the internal mode, output port enable & card power enable.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 2.2 PCCARD CONFIGURATION & STATUS REGISTER Register Address R/W PCCARD_CFG 0x4B801820 R/W PCCARD_CFG Reserved Description PCCARD_CFG is used to set the configuration & read the status of card.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 2.3 PCCARD INTERRUPT MASK & SOURCE REGISTER Register Address R/W PCCARD_INT 0x4B801824 R/W PCCARD_INT Reserved Bits [31:11] INTMSK_ERR_ N [10] INTMSK_IREQ [9] Description Reset Value PCCARD_INT is interrupt source & interrupt mask register.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 2.4 PCCARD_ATTR REGISTER Register Address R/W PCCARD_ATT R 0x4B801828 R/W PCCARD_ATTR Description PCCARD_ATTR is used to set the card access timing.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 2.6 PCCARD_COMM REGISTER Register Address R/W PCCARD_COM M 0x4B801830 R/W PCCARD_COMM Description PCCARD_COMM is used to set the card access timing.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 2.7 ATA_CONTROL REGISTER Register Address R/W ATA_CONTROL 0x4B801900 R/W ATA_CONTROL Reserved clk_down_ready Description ATA Control register Bits [31:2] [1] Reset Value Description 0x0000_0002 R/W Reset Value Reserved bits R 0x0 Status for clock down R 0x1 R/W 0x0 This bit is asserted in idle state when ATA_CONTROL bit [0] is zero.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 2.9 ATA_COMMAND REGISTER Register Address R/W ATA_COMMAND 0x4B801908 R/W ATA_COMMAND Description Reset Value ATA Command register Bits Description Reserved [31:2] Reserved bits xfr_command [1:0] ATA transfer command 0x0000_0000 R/W Reset Value R 0x0 R/W 0x0 Four command types (START, STOP, ABORT and CONTINUE) are supported for data transfer control. The “START” command is used to start data transfer.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 2.10 ATA_SWRST REGISTER Register Address R/W ATA_SWRST 0x4B80190C R/W ATA_SWRST Description ATA S/W RESET register Bits Reserved [31:1] ata_swrstn [0] Reset Value Description Reserved bits Software reset for the ATA host 0x0000_0000 R/W Reset Value R 0x0 R/W 0x0 0 = No reset 1 = Software reset for all ATA host module. After software reset, to continue transfer, user must configure all registers of host controller and device registers. 2.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 2.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 2.13 ATA_CFG REGISTER Register Address R/W ATA_CFG 0x4B801918 R/W ATA_CFG Reserved sbuf_empty_ mode Bits [31:9] [8] Description Reset Value ATA Configuration register Description Reserved bits Determines whether to continue automatically when source buffer is empty. This bit should not be changed during runtime operation.
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S3C2450X RISC MICROPROCESSOR ATA_CFG Bits CF CONTROLLER Description R/W Reset Value R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 1 = Active low dma_dir [4] DMA transfer direction 0 = Host read data from device 1 = Host write data to device ata_class [3:2] ATA transfer class select 0 = Transfer class is PIO 1 = Transfer class is PIO DMA 2,3 = Reserved ata_iordy_en [1] Determines whether IORDY input can extend data transfer.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 2.14 ATA_PIO_TIME REGISTER Register Address R/W Description Reset Value ATA_PIO_TIME 0x4B80192C R/W ATA PIO Timing Control register 0x0001_C23 8 ATA_PIO_TIME Bits Description Reserved [31:20] Reserved bits pio_teoc [19:12] PIO timing parameter, teoc, end of cycle time It shall not have zero value.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 2.17 ATA_TBUF_START REGISTER Register ATA_TBUF_ START ATA_TBUF_ START Address R/W 0x4B80193C R/W Bits Description Reset Value Start address of track buffer Description track_buffer_ start [31:2] Start address of track buffer (4byte unit) Reserved [1:0] Reserved bits 0x0000_0000 R/W Reset Value R/W 0x00000000 R 0x0 2.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 2.19 ATA_SBUF_START REGISTER Register ATA_SBUF_ START Address R/W 0x4B801944 R/W Description Reset Value Start address of source buffer ATA_SBUF_ START Bits Description src_buffer_start [31:2] Start address of source buffer (4byte unit) Reserved [1:0] Reserved bits 0x0000_0000 R/W Reset Value R/W 0x00000000 R 0x0 2.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 2.21 ATA_CADDR_TBUF REGISTER Register ATA_CADDR_ TBUF ATA_CADDR_ TBUF Address R/W 0x4B80194C R/W Bits Description Reset Value Current address of track buffer Description track_buf_ cur_adr [31:2] Current address of track buffer Reserved [1:0] Reserved bits 0x0000_0000 R/W Reset Value R/W 0x00000000 R 0x0 2.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 2.24 ATA_PIO_FED REGISTER Register Address R/W ATA_PIO_FED 0x4B801958 W ATA_PIO_FED Bits Description Reset Value 8bit PIO device feature/error register Description 0x0000_0000 R/W Reset Value Reserved [31:8] Reserved bits R 0x0 pio_dev_fed [7:0] 8-bit PIO device feature/error (command block) register W 0x00 NOTE: pio_dev_fed can be read by accessing register ATA_PIO_RDATA 2.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 2.27 ATA_PIO_LMR REGISTER Register Address R/W ATA_PIO_LMR 0x4B801964 W ATA_PIO_LMR Bits Description Reset Value 8-bit PIO device LBA middle register Description 0x0000_0000 R/W Reset Value Reserved [31:8] Reserved bits R 0x0 pio_dev_lmr [7:0] 8-bit PIO device LBA middle (command block) register W 0x00 NOTE: pio_dev_lmr can be read by accessing register ATA_PIO_RDATA 2.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR 2.30 ATA_PIO_CSD REGISTER Register Address R/W ATA_PIO_CSD 0x4B801970 W ATA_PIO_CSD Bits Description Reset Value 8-bit PIO device command/status register Description 0x0000_0000 R/W Reset Value Reserved [31:8] Reserved bits R 0x0 pio_dev_csd [7:0] 8-bit PIO device command/status (command block) register W 0x00 NOTE: pio_dev_csd can be read by accessing register ATA_PIO_RDATA 2.
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S3C2450X RISC MICROPROCESSOR CF CONTROLLER 2.33 BUS_FIFO_STATUS REGISTER Register BUS_FIFO_ STATUS BUS_FIFO_ STATUS Address 0x4B801990 R/W R Description Reset Value BUS FIFO status register Bits Description 0x0000_0000 R/W Reset Value Reserved [31:19] Reserved bits R 0x0 bus_state[2:0] [18:16] 3’b000 : IDLE R 0x00 Another value is in operation.
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CF CONTROLLER S3C2450X RISC MICROPROCESSOR NOTES 8-30
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S3C2450X RISC MICROPROCESSOR 9 DMA CONTROLLER DMA CONTROLLER 1 OVERVIEW S3C2450 supports eight-channel DMA (Bridge DMA or peripheral DMA) controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions.
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DMA CONTROLLER S3C2450X RISC MICROPROCESSOR 2 DMA REQUEST SOURCES Each channel of DMA controller can select one source among 27 DMA sources if H/W DMA request mode is selected by REQSEL register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.) The 27 DMA sources for each channel are as follows. Table 9-1.
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S3C2450X RISC MICROPROCESSOR DMA CONTROLLER 3 DMA OPERATION The details of DMA operation can be explained using three-state FSM (finite state machine) as follows: State-1. As an initial state, it waits for the DMA request. If it comes, go to state-2. At this state, DMA ACK and INT REQ are 0. State-2. In this state, DMA ACK becomes 1 and the counter (CURR_TC) is loaded from DCON[19:0] register. Note that DMA ACK becomes 1 and remains 1 until it is cleared later. State-3.
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DMA CONTROLLER S3C2450X RISC MICROPROCESSOR 3.1 EXTERNAL DMA DREQ/DACK PROTOCOL There are four types of external DMA request/acknowledge protocols. Each type defines how the signals like DMA request and acknowledge are related to these protocols. 3.1.1 Basic DMA Timing The DMA service means paired Reads and Writes cycles during DMA operation, which is one DMA operation. The Figure 9-1 shows the basic Timing in the DMA operation of the S3C2450.
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S3C2450X RISC MICROPROCESSOR DMA CONTROLLER Demand/Handshake Mode Comparison − Related to the Protocol between XnXDREQ and XnXDACK These are two different modes related to the protocol between XnXDREQ and XnXDACK. Figure 9-2 shows the differences between these two modes i.e., Demand and Handshake modes. At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ. 3.1.2 Demand mode • If XnXDREQ remains asserted, the next transfer starts immediately.
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DMA CONTROLLER S3C2450X RISC MICROPROCESSOR 3.1.4 Transfer Size • There are two different transfer sizes; single and Burst 4. • DMA holds the bus firmly during the transfer of these chunk of data, thus other bus masters can not get the bus. 3.1.5 Burst 4 Transfer Size 4 sequential Reads and 4 sequential Writes are performed in the Burst 4 Transfer. NOTE Single Transfer size: One read and one write are performed. XSCLK XnXDREQ XnXDACK Double synch 3 cycles Read Read Read Figure 9-3.
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S3C2450X RISC MICROPROCESSOR DMA CONTROLLER 3.2 EXAMPLES OF POSSIBLE CASES 3.2.1 Single service, Demand Mode, Single Transfer Size The assertion of XnXDREQ is need for every unit transfer (Single service mode), the operation continues while the XnXDREQ is asserted(Demand mode), and one pair of Read and Write(Single transfer size) is performed. XSCLK XnXDREQ XnXDACK Double synch Read Write Read Write Figure 9-4.
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DMA CONTROLLER S3C2450X RISC MICROPROCESSOR 4 DMA SPECIAL REGISTERS There are 10 control registers for each DMA channel. (Since there are six channels, the total number of control registers is 60.) Seven of them are to control the DMA transfer, and other three are to see the status of DMA controller. The details of those registers are as follows. 4.
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S3C2450X RISC MICROPROCESSOR DMA CONTROLLER 4.
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DMA CONTROLLER S3C2450X RISC MICROPROCESSOR 4.
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S3C2450X RISC MICROPROCESSOR DMA CONTROLLER 4.
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DMA CONTROLLER S3C2450X RISC MICROPROCESSOR 4.
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S3C2450X RISC MICROPROCESSOR DCONn Bit SERVMODE [27] DMA CONTROLLER Description Select the service mode between single service mode and whole service mode. Initial State 0 0 = Single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request. 1 = Whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0. In this mode, additional request is not required.
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DMA CONTROLLER S3C2450X RISC MICROPROCESSOR 4.
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S3C2450X RISC MICROPROCESSOR DMA CONTROLLER 4.
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DMA CONTROLLER S3C2450X RISC MICROPROCESSOR 4.
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S3C2450X RISC MICROPROCESSOR DMA CONTROLLER 4.
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DMA CONTROLLER S3C2450X RISC MICROPROCESSOR NOTES 9-18
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S3C2450X RISC MICROPROCESSOR 10 INTERRUPT CONTROLLER INTERRUPT CONTROLLER 1 OVERVIEW The interrupt controller in the S3C2450 receives the request from 59 interrupt sources. These interrupt sources are provided by internal peripherals such as the DMA controller, the UART, IIC, and others. In these interrupt sources, the UARTn and EINTn interrupts are 'OR'ed to the interrupt controller.
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR The interrupt controller has two groups of interrupt sources, and first group has always higher priority than the other group. Actually, we made this interrupt controller using by two interrupt controllers. The nRIQ of ARM926EJ is connected with ‘AND’ of nIRQs of each interrupt controller. The nFIQ is just same. Figure 10-2.
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S3C2450X RISC MICROPROCESSOR INTERRUPT CONTROLLER 1.1 INTERRUPT CONTROLLER OPERATION 1.1.1 F-bit and I-bit of Program Status Register (PSR) If the F-bit of PSR in ARM926EJ CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not accept the Interrupt Request (IRQ) from the interrupt controller.
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 1.2 INTERRUPT SOURCES The interrupt controller supports 51 interrupt sources as shown in the table below.
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S3C2450X RISC MICROPROCESSOR Sources INTERRUPT CONTROLLER Descriptions Arbiter Group INT_UART0 UART0 Interrupt (ERR, RXD, and TXD) ARB5 INT_IIC0 IIC 0 interrupt ARB4 INT_USBH USB Host interrupt ARB4 INT_USBD USB Device interrupt ARB4 INT_NAND NAND Flash Controller interrupt ARB4 INT_UART1 UART1 Interrupt (ERR, RXD, and TXD) ARB4 INT_SPI0 High speed SPI 0 interrupt ARB4 INT_SDI0 High Speed SDMMC 0 interrupt ARB3 INT_SDI1 High Speed SDMMC 1 interrupt ARB3 INT_CFCON CFCON inter
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 1.3 INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in Figure 10-2 below. Figure 10-3.
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S3C2450X RISC MICROPROCESSOR INTERRUPT CONTROLLER 1.4 INTERRUPT PRIORITY We have two groups of arbiters. One group is ARBITER0~ARBITER5, and the other is ARMBITER6~ARBITER11. The former group has higher priority than the latter group. And priority of arbiters in each group can be set as below separately.
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 2 INTERRUPT CONTROLLER SPECIAL REGISTERS There are following control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, interrupt pending register, interrupt offset register, sub-source pending register and sub-mask register. All the interrupt requests from the interrupt sources are first registered in the source pending register.
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S3C2450X RISC MICROPROCESSOR Register Address INTERRUPT CONTROLLER R/W Description Reset Value request. INTMOD 2 0X4A000044 R/W Interrupt mode regiseter for group 2. 0x00000000 0 = IRQ mode 1 = FIQ mode INTMSK2 0X4A000048 R/W Determine which interrupt source of group 2 is masked. The masked interrupt source will not be serviced. 0xFFFFFFFF 0 = Interrupt service is available. 1 = Interrupt service is masked. INTPND2 0X4A000050 R/W Indicate the interrupt request status for group 2.
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 2.1 SOURCE PENDING (SRCPND) REGISTER The SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. Accordingly, this register indicates which interrupt source is waiting for the request to be serviced.
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S3C2450X RISC MICROPROCESSOR SRCPND 1 INTERRUPT CONTROLLER Bit Description Initial State INT_UART3 [18] 0 = Not requested, 1 = Requested 0 INT_DMA [17] 0 = Not requested, 1 = Requested 0 INT_LCD [16] 0 = Not requested, 1 = Requested 0 INT_UART2 [15] 0 = Not requested, 1 = Requested 0 INT_TIMER4 [14] 0 = Not requested, 1 = Requested 0 INT_TIMER3 [13] 0 = Not requested, 1 = Requested 0 INT_TIMER2 [12] 0 = Not requested, 1 = Requested 0 INT_TIMER1 [11] 0 = Not request
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 2.2 INTERRUPT MODE (INTMOD) REGISTER This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode. Otherwise, it is processed in the IRQ mode (normal interrupt). Note that only one interrupt source can be serviced in the FIQ mode in the interrupt controller (you should use the FIQ mode only for the urgent interrupt).
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S3C2450X RISC MICROPROCESSOR INTMOD1 INTERRUPT CONTROLLER Bit Description Initial State INT_WDT/AC97 [9] 0 = IRQ, 1 = FIQ 0 INT_TICK [8] 0 = IRQ, 1 = FIQ 0 nBATT_FLT [7] 0 = IRQ, 1 = FIQ 0 INT_CAM [6] 0 = IRQ, 1 = FIQ 0 EINT8_23 [5] 0 = IRQ, 1 = FIQ 0 EINT4_7 [4] 0 = IRQ, 1 = FIQ 0 EINT3 [3] 0 = IRQ, 1 = FIQ 0 EINT2 [2] 0 = IRQ, 1 = FIQ 0 EINT1 [1] 0 = IRQ, 1 = FIQ 0 EINT0 [0] 0 = IRQ, 1 = FIQ 0 INTMOD2 Bit Description Initial State INT_I2S1 [7]
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 2.3 INTERRUPT MASK (INTMSK) REGISTER This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not service the interrupt request from the corresponding interrupt source (note that even in such a case, the corresponding bit of SRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced.
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S3C2450X RISC MICROPROCESSOR INTMSK1 Bit INTERRUPT CONTROLLER Description Initial State INT_TICK [8] 0 = Service available, 1 = Masked 1 nBATT_FLT [7] 0 = Service available, 1 = Masked 1 INT_CAM [6] 0 = Service available, 1 = Masked 1 EINT8_23 [5] 0 = Service available, 1 = Masked 1 EINT4_7 [4] 0 = Service available, 1 = Masked 1 EINT3 [3] 0 = Service available, 1 = Masked 1 EINT2 [2] 0 = Service available, 1 = Masked 1 EINT1 [1] 0 = Service available, 1 = Masked
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 2.4 INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority. Since the INTPND register is located after the priority logic, only one bit can be set to 1, and that interrupt request generates IRQ to CPU.
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S3C2450X RISC MICROPROCESSOR INTPND1 INTERRUPT CONTROLLER Bit Description Initial State INT_UART3 [18] 0 = Not requested, 1 = Requested 0 INT_DMA [17] 0 = Not requested, 1 = Requested 0 INT_LCD [16] 0 = Not requested, 1 = Requested 0 INT_UART2 [15] 0 = Not requested, 1 = Requested 0 INT_TIMER4 [14] 0 = Not requested, 1 = Requested 0 INT_TIMER3 [13] 0 = Not requested, 1 = Requested 0 INT_TIMER2 [12] 0 = Not requested, 1 = Requested 0 INT_TIMER1 [11] 0 = Not requeste
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 2.5 INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt offset register shows, which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND.
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S3C2450X RISC MICROPROCESSOR INT Source for group 2 INTERRUPT CONTROLLER The OFFSET Value INT Source for group 2 The OFFSET Value Reserved 19 Reserved 3 Reserved 18 Reserved 2 Reserved 17 INT_IIC1 1 Reserved 16 INT_2D 0 NOTE: FIQ mode interrupt does not affect the INTOFFSET register as the register is available only for IRQ mode interrupt.
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 2.6 SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data. The bit positions corresponding to those that are set to 0 in the data remains as they are. Register SUBSRCPND Address R/W 0X4A000018 R/W Description Reset Value Indicate the interrupt request status.
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S3C2450X RISC MICROPROCESSOR SUBSRCPND Bit INTERRUPT CONTROLLER Description SRCPND Initial State SUBINT_ERR1 [5] 0 = Not requested, 1 = Requested SUBINT_TXD1 [4] 0 = Not requested, 1 = Requested 0 SUBINT_RXD1 [3] 0 = Not requested, 1 = Requested 0 SUBINT_ERR0 [2] 0 = Not requested, 1 = Requested SUBINT_TXD0 [1] 0 = Not requested, 1 = Requested 0 SUBINT_RXD0 [0] 0 = Not requested, 1 = Requested 0 INT_UART1 INT_UART0 0 0 10-21
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 2.7 INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 27 bits each of which is related to an interrupt source. If a specific bit is set to 1, the interrupt request from the corresponding interrupt source is not serviced by the CPU (note that even in such a case, the corresponding bit of the SUBSRCPND register is set to 1). If the mask bit is 0, the interrupt request can be serviced.
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S3C2450X RISC MICROPROCESSOR INTSUBMASK Bit INTERRUPT CONTROLLER Description INTMASK Initial State SUBINT_RXD2 [6] 0 = Service available, 1 = Masked 1 SUBINT_ERR1 [5] 0 = Service available, 1 = Masked SUBINT_TXD1 [4] 0 = Service available, 1 = Masked 1 SUBINT_RXD1 [3] 0 = Service available, 1 = Masked 1 SUBINT_ERR0 [2] 0 = Service available, 1 = Masked SUBINT_TXD0 [1] 0 = Service available, 1 = Masked 1 SUBINT_RXD0 [0] 0 = Service available, 1 = Masked 1 INT_UART1 INT_UART0
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR 2.
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S3C2450X RISC MICROPROCESSOR INTERRUPT CONTROLLER PRIORITY_MODE1 Bit Description ARB_MODE3 [15] Arbiter 3 group priority mode selection Initial State 0 0 = Fixed ends & Rotate middle 1 = Rotate all ARB_SEL3 [14:12] Arbiter 3 group priority order set 0 1) ARB_MODE3 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 2) ARB_MODE3 = 1’b1 000 = REQ 0-1-2-3-4-5 001 = REQ 1-2-3-4-5-0 010 = REQ 2-3-4-5-0-1 011 = REQ 3-4-5-0-1-2 100 = REQ 4-5-0-1-2-3 101 = REQ 5-0
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INTERRUPT CONTROLLER PRIORITY_MODE1 S3C2450X RISC MICROPROCESSOR Bit Description Initial State 101 = REQ 5-0-1-2-3-4 ARB_MODE0 [3] Arbiter 0 group priority mode selection 0 0 = Fixed ends & Rotate middle ARB_SEL0 [2:0] Arbiter 0 group priority order set 1) ARB_MODE0 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 10-26 0
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S3C2450X RISC MICROPROCESSOR PRIORITY_MODE2 Bit ARB_MODE13 [27] INTERRUPT CONTROLLER Description Arbiter 13 group priority mode selection Initial State 0 0 = Fixed ends & Rotate middle 1 = Rotate all ARB_SEL13 [26:24] Arbiter 13 group priority order set 0 1) ARB_MODE13 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 2) ARB_MODE13 = 1’b1 000 = REQ 0-1-2-3-4-5 001 = REQ 1-2-3-4-5-0 010 = REQ 2-3-4-5-0-1 011 = REQ 3-4-5-0-1-2 100 = REQ 4-5-0-1-2-3 101 = RE
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INTERRUPT CONTROLLER PRIORITY_MODE2 Bit S3C2450X RISC MICROPROCESSOR Description Initial State 1) ARB_MODE10 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 2) ARB_MODE10 = 1’b1 000 = REQ 0-1-2-3-4-5 001 = REQ 1-2-3-4-5-0 010 = REQ 2-3-4-5-0-1 011 = REQ 3-4-5-0-1-2 100 = REQ 4-5-0-1-2-3 101 = REQ 5-0-1-2-3-4 ARB_MODE9 [11] Arbiter 9 group priority mode selection 0 0 = Fixed ends & Rotate middle 1 = Rotate all ARB_SEL9 [10:8] Arbiter 9 group priority ord
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S3C2450X RISC MICROPROCESSOR PRIORITY_MODE2 ARB_SEL7 INTERRUPT CONTROLLER Bit [2:0] Description Arbiter 7 group priority order set Initial State 0 1) ARB_MODE7 = 1’b0 00 = REQ 0-1-2-3-4-5 01 = REQ 0-2-3-4-1-5 10 = REQ 0-3-4-1-2-5 11 = REQ 0-4-1-2-3-5 2.
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INTERRUPT CONTROLLER S3C2450X RISC MICROPROCESSOR PRIORITY_UPDATE2 Bit ARB_UPDATE13 [6] Description Arbiter 13 group priority rotate enable Initial State 1 0 = Priority does not rotate 1 = Priority rotate enable ARB_UPDATE12 [5] Arbiter 12 group priority rotate enable 1 0 = Priority does not rotate 1 = Priority rotate enable ARB_UPDATE11 [4] Arbiter 11 group priority rotate enable 1 0 = Priority does not rotate 1 = Priority rotate enable ARB_UPDATE10 [3] Arbiter 10 group priority rotate en
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S3C2450X RISC MICROPROCESSOR 11 I/O PORTS I/O PORTS 1 OVERVIEW S3C2450 has 174 multi-functional input/output port pins and there are 12 ports as shown below: • Port A(GPA) : 27-output port • Port B(GPB) : 11-input/output port • Port C(GPC) : 16-input/output port • Port D(GPD) : 16-input/output port • Port E(GPE) : 16-input/output port • Port F(GPF) : 8-input/output port • Port G(GPG) : 16-input/output port • Port H(GPH) : 15-input/output port • Port J(GPJ) : 16-input/output port • Por
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I/O PORTS S3C2450X RISC MICROPROCESSOR Table 11-1.
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S3C2450X RISC MICROPROCESSOR I/O PORTS Table 11-1.
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I/O PORTS S3C2450X RISC MICROPROCESSOR Table 11-1.
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S3C2450X RISC MICROPROCESSOR I/O PORTS Table 11-1.
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I/O PORTS S3C2450X RISC MICROPROCESSOR Table 11-1.
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S3C2450X RISC MICROPROCESSOR I/O PORTS Table 11-1.
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I/O PORTS S3C2450X RISC MICROPROCESSOR Table 11-1.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 2 PORT CONTROL DESCRIPTIONS 2.1 PORT CONFIGURATION REGISTER (GPACON-GPMCON) In S3C2450, most of the pins are multiplexed pins. So, It is determined which function is selected for each pins. The GPxCON(port control register) determines which function is used for each pin. If GPF0 – GPF7, GPG0 – GPG7 is used for the wakeup signal in Sleep/Stop/DeepStop mode, these ports must be configured in EINT. 2.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3 I/O PORT CONTROL REGISTER 3.
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S3C2450X RISC MICROPROCESSOR GPADAT Reserved GPA[27:0] Bit [31:28] [27:0] I/O PORTS Description Reserved When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read. NOTE: GPA10 is excluded in data output mode.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.
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S3C2450X RISC MICROPROCESSOR I/O PORTS GPBUDP Bit Description Reserved [31:22] Reserved GPBUDP10 [21:20] [CPU:CPD] ~ ~ GPBUDP0 [1:0] 00 = pull-up/down disable 01 = pull-down enable 10 = pull-up enable 11 = not-available GPBSEL Bit Description Reserved [31:5] GPB10SEL [4] 0 = GPB10 1 = I2SSDO_2 GPB9SEL [3] 0 = GPB9 1 = I2SSDO_1 GPB8SEL [2] 0 = GPB8 1 = I2CSCL GPB7SEL [1] 0 = GPB7 1 = I2CSDA GPB6SEL [0] 0 = GPB6 1 = RTCK Reserved 11-13
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.
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S3C2450X RISC MICROPROCESSOR I/O PORTS GPCDAT Bit Description Reserved [31:16] Reserved GPC[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.
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S3C2450X RISC MICROPROCESSOR I/O PORTS GPDDAT Bit Description Reserved [31:16] Reserved GPD[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin state. When the port is configured as output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.
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S3C2450X RISC MICROPROCESSOR I/O PORTS GPEDAT Bit Description Reserved [31:16] Reserved GPE[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as a functional pin, the undefined value will be read.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.6 PORT F CONTROL REGISTERS (GPFCON, GPFDAT, GPFUDP) If GPF0 − GPF7 will be used for wake-up signals from Sleep/Stop/Deep Stop mode, the ports will be set in EINT.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.7 PORT G CONTROL REGISTERS (GPGCON, GPGDAT, GPGUDP) If GPG0–GPG7 will be used for wake-up signals from Sleep/Stop/Deep Stop mode, the ports will be set in EINT.
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I/O PORTS S3C2450X RISC MICROPROCESSOR GPGDAT Bit Description Reserved [31:16] Reserved GPG[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.
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I/O PORTS S3C2450X RISC MICROPROCESSOR GPHDAT Bit Description Reserved [31:15] Reserved GPH[14:0] [14:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.
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I/O PORTS S3C2450X RISC MICROPROCESSOR GPJDAT Bit Description Reserved [31:16] Reserved GPJ[15:0] [15:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.
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I/O PORTS S3C2450X RISC MICROPROCESSOR GPKDAT Bit GPK[15:0] [31:0] Description When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.
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I/O PORTS S3C2450X RISC MICROPROCESSOR GPLDAT Bit Description Reserved [31:15] Reserved GPL[14:0] [14:0] When the port is configured as an input port, the corresponding bit is the pin state. When the port is configured as an output port, the pin state is the same as the corresponding bit. When the port is configured as functional pin, the undefined value will be read.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.13 MISCELLANEOUS CONTROL REGISTER (MISCCR) In Sleep mode, the data bus(SD[15:0] or RD[15:0] can be set as Hi-Z and Output ‘0’ state. But, because of the characteristics of IO pad, the data bus pull-up/down resisters have to be turned on or off to reduce the power consumption. SD[15:0] or RD[15:0] pin pull-up/down resisters can be controlled by MISCCR register. Pads related USB are controlled by this register for USB host, or for USB device.
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S3C2450X RISC MICROPROCESSOR MISCCR Bit CLKSEL0 * [6:4] I/O PORTS Description Select source clock with CLKOUT0 pad Reset Value 010 000 = MPLL INPUT Clock(XTAL) 001 = EPLL output 010 = FCLK(ARMCLK) 011 = HCLK 100 = PCLK 101 = DCLK0 (Divided PCLK) 110 = OSC To PLL INPUT Clock 111 = Reserved Reserved [3:0] Reserved 0 NOTES: 1. User must set first MISCCR[31] = 1’b1 when use the high speed SPI. 2. We recommend not using this output pad to other device’s pll clock source.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.14 DCLK CONTROL REGISTERS (DCLKCON) Register Address R/W Description DCLKCON 0x56000084 R/W DCLKCON Bit Reserved [31:28] Reserved DCLK1CMP [27:24] DCLK1 compare value clock toggle value.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.15 EXTINTn (External Interrupt Control Register n) The 8 external interrupts can be requested by various Signalling methods. The EXTINT register configures the Signalling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter.
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I/O PORTS S3C2450X RISC MICROPROCESSOR EXTINT0 Bit EINT3 [14:12] Reserved [11] EINT2 [10:8] Reserved [7] EINT1 [6:4] Reserved [3] EINT0 [2:0] 11-36 Description Setting the signalling method of the EINT3. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved Setting the signalling method of the EINT2.
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S3C2450X RISC MICROPROCESSOR EXTINT1 Bit Reserved [31] EINT15 [30:28] Reserved [27] EINT14 [26:24] Reserved [23] EINT13 [22:20] Reserved [19] EINT12 [18:16] Reserved [15] EINT11 [14:12] Reserved [11] EINT10 [10:8] Reserved [7] EINT9 [6:4] Reserved [3] EINT8 [2:0] I/O PORTS Description Reserved Setting the signaling method of the EINT15.
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I/O PORTS S3C2450X RISC MICROPROCESSOR EXTINT2 Bit FLTEN23 [31] Description Filter enable for EINT23 Reset Value 0 0 = Filter Enable 1 = Filter Disable EINT23 [30:28] Setting the signaling method of the EINT23. 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered FLTEN22 [27] 000 001 = High level 10x = Rising edge triggered Filter Enable for EINT22 0 0 = Filter Enable 1 = Filter Disable EINT22 [26:24] Setting the signaling method of the EINT22.
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S3C2450X RISC MICROPROCESSOR EXTINT2 Bit FLTEN17 [7] EINT17 [6:4] I/O PORTS Description Filter enable for EINT17 0 = Filter Enable FLTEN16 EINT16 [3] [2:0] 0 1 = Filter Disable Setting the signalling method of the EINT17. 000 = Low level 01x = Falling edge triggered 11x = Both edge triggered Filter enable for EINT16 0 = Filter Enable 000 001 = High level 10x = Rising edge triggered 0 1 = Filter Disable Setting the ٛsignalling method of the EINT16.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.16 EINTFLTn (External Interrupt Filter Register n) To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of the noise filter.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.
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S3C2450X RISC MICROPROCESSOR I/O PORTS DSC1 Bit Description Reset Value Reserved [31:28] Reserved 0x0 DSC_nSCLK [27:26] nSCLK drive strength. 00 = 4.9mA 01 = 9.8mA 10 = 14.8mA 11 = 19.7mA 10 DSC_SCLK [25:24] SCLK drive strength. 00 = 4.9mA 01 = 9.8mA 10 = 14.8mA 11 = 19.7mA 10 DSC_SCKE [23:22] SCKE Drive strength. 00 = 4.9mA 01 = 9.8mA 10 = 14.8mA 11 = 19.7mA 10 Reserved [21:20] Reserved 10 DSC_nSWE [19:18] nSWE drive strength. 00 = 4.9mA 01 = 9.8mA 10 = 14.8mA 11 = 19.
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I/O PORTS S3C2450X RISC MICROPROCESSOR DSC2 Bit Reserved [31:28] Reserved 0x0 DSC_nFCE [27:26] nFCE drive strength. 00 = 5.2mA 01 = 10.5mA 10 = 15.7mA 11 = 21.0mA 10 DSC_nFRE [25:24] nFRE drive strength. 00 = 5.2mA 01 = 10.5mA 10 = 15.7mA 11 = 21.0mA 10 DSC_nFWE [23:22] nFWE Drive strength. 00 = 5.2mA 01 = 10.5mA 10 = 15.7mA 11 = 21.0mA 10 DSC_ALE [21:20] ALE drive strength. 00 = 5.2mA 01 = 10.5mA 10 = 15.7mA 11 = 21.0mA 10 DSC_CLE [19:18] CLE drive strength. 00 = 5.2mA 01 = 10.
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S3C2450X RISC MICROPROCESSOR DSC3 Bit Reserved [31:10] DSC_LCD2 I/O PORTS Description Reset Value Reserved 0x0 [9:8] LCD_VD[23:16] drive strength. 00 = 2.6mA 01 = 5.2mA 10 = 7.8mA 11 = 10.5mA 10 DSC_LCD1 [7:6] LCD_VD[15:8] drive strength. 00 = 2.6mA 01 = 5.2mA 10 = 7.8mA 11 = 10.5mA 10 DSC_LCD0 [5:4] LCD_VD[7:0] drive strength. 00 = 2.6mA 01 = 5.2mA 10 = 7.8mA 11 = 10.5mA 10 DSC_HS_MMC [3:2] HS_MMC drive strength. 00 = 2.6mA 01 = 5.2mA 10 = 7.8mA 11 = 10.
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I/O PORTS S3C2450X RISC MICROPROCESSOR 3.
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S3C2450X RISC MICROPROCESSOR I/O PORTS 3.
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I/O PORTS S3C2450X RISC MICROPROCESSOR PDSMCON Bit PSC_RADDRH [5:4] Description RADDR[25:16]/GPA[GPA10:1] pin status (inactive : “0”) 00 = output 0 10 = Hi-Z 11-50 Reset Value 00 01 = output 1 11 = Not-Available PSC_RADDRL [3:2] RADDR[15:1] pin status (inactive : “0”) 00 = output 0 01 = output 1 10 = Hi-Z 11 = Not-Available 00 PSC_RADDR0 [1:0] RADDR[0]/GPA[0] pin status (inactive : “0”) 00 = output 0 01 = output 1 10 = Hi-Z 11 = Not-Available 00
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S3C2450X RISC MICROPROCESSOR I/O PORTS 4 GPIO ALIVE & SLEEP PART Alive Sleep PAD GPF[7:0], GPG[7:0] GPA, GPB, GPC, GPD, GPE, GPG[15:8], GPH, GPJ, GPK, GPL ,GPM SFR GPACON[27;0], GPADAT[27:0] All registers except alive SFR GPFCON[15;0], GPFDAT[7:0], GPFUDP[15:0] GP*CON, GP*DAT, GP*UDP GPGCONL[15:0], GPGDATL[7:0], GPGUDPL[15:0] GPKCON[31:0], GPKDAT[15:0], GPKUDP[31:0] EXTINT0[31:0], EXINT1[31:0] PDDMCON, PDSMCON 11-51
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I/O PORTS S3C2450X RISC MICROPROCESSOR NOTES 11-52
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S3C2450X RISC MICROPROCESSOR 12 WATCHDOG TIMER WATCHDOG TIMER 1 OVERVIEW The S3C2450 watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. The watchdog timer generates the reset signal. It can be used as a normal 16bit interval timer to request interrupt service. Advantage in using WDT instead of PWM timer is that WDT generates the reset signal. 1.
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WATCHDOG TIMER S3C2450X RISC MICROPROCESSOR 2 WATCHDOG TIMER OPERATION 2.1 BLOCK DIAGRAM Figure 12-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again.
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S3C2450X RISC MICROPROCESSOR WATCHDOG TIMER 2.3 CONSIDERATION OF DEBUGGING ENVIRONMENT When the S3C2450 is in debug mode using Embedded ICE, the watchdog timer must not operate. The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal (DBGACK signal). Once the DBGACK signal in CPU core is asserted, the reset output of the watchdog timer is not activated as the watchdog timer is expired.
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WATCHDOG TIMER S3C2450X RISC MICROPROCESSOR 3 WATCHDOG TIMER SPECIAL REGISTERS 3.1 WATCHDOG TIMER CONTROL (WTCON) REGISTER The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. The Watchdog timer is used to resume the S3C2450 restart on malfunction after its power on.
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S3C2450X RISC MICROPROCESSOR WATCHDOG TIMER 3.2 WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) will drive the first time-out. In this case, the value of WTDAT will be automatically reloaded into WTCNT.
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WATCHDOG TIMER S3C2450X RISC MICROPROCESSOR NOTES 12-6
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S3C2450X RISC MICROPROCESSOR 13 PWM TIMER PWM TIMER 1 OVERVIEW The S3C2450 has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device. The timer 0 and 1 share an 8-bit prescaler, while the timer 2, 3 and 4 share other 8-bit prescaler.
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PWM TIMER S3C2450X RISC MICROPROCESSOR TOUT0 TCMPB0 TCNTB0 8-Bit Prescaler 1/2 1/4 1/8 1/16 TCLK Clock Divider Control Logic0 TCMPB1 Dead Zone Clock Divider 5:1 MUX TCNTB2 TOUT2 Control Logic2 TCMPB3 5:1 MUX 8-Bit Prescaler TCNTB1 Control Logic1 TCMPB2 1/2 1/4 1/8 1/16 TCLK Dead Zone TOUT1 5:1 MUX PCLK 5:1 MUX Dead Zone Generator TCNTB3 Control Logic3 TOUT3 5:1 MUX TCNTB4 Control Logic4 Figure 13-1.
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S3C2450X RISC MICROPROCESSOR PWM TIMER 2 PWM TIMER OPERATION 2.1 PRESCALER & DIVIDER An 8-bit prescaler and a 4-bit divider make the following output frequencies: 4-bit Divider Settings Minimum Resolution Maximum Resolution Min. Interval Max. Interval (prescaler = 0) (prescaler = 255) (TCNTBn = 1) (TCNTBn = 65535) 1/2 (PCLK = 50 MHz) 0.0400 us (25.000 MHz) 10.2400 us (97.6562 kHz) 0.0800 us 0.6710 sec 1/4 (PCLK = 50 MHz) 0.0800 us (12.500 MHz) 20.4800 us (48.8281 kHz) 0.1600 us 1.
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PWM TIMER S3C2450X RISC MICROPROCESSOR 2.2 BASIC TIMER OPERATION Figure 13-2. Timer Operations A timer (except the timer ch-4) has TCNTBn, TCNTn, TCMPBn and TCMPn. The TCNTBn and the TCMPBn are loaded into the TCNTn and the TCMPn when the timer reaches 0. When the TCNTn reaches 0, an interrupt request will occur if the interrupt is enabled. NOTE TCNTn and TCMPn are the names of the internal registers. (16bit Internal down-counter (register) and 16bit internal compare register, respectively.
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S3C2450X RISC MICROPROCESSOR PWM TIMER 2.3 AUTO RELOAD & DOUBLE BUFFERING S3C2450 PWM Timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully. The timer value can be written into Timer Count Buffer register (TCNTBn) and the current counter value of the timer can be read from Timer Count Observation register (TCNTOn).
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PWM TIMER S3C2450X RISC MICROPROCESSOR 2.4 TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the internal down-counter(TCNTn) reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit. The following steps describe how to start a timer: 1. Write the initial value into TCNTBn and TCMPBn. 2. Set the manual update bit of the corresponding timer.
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S3C2450X RISC MICROPROCESSOR PWM TIMER 2.5 TIMER OPERATION 1 2 3 4 6 7 9 10 TOUTn 50 110 40 5 40 20 60 8 11 Figure 13-4. Example of a Timer Operation The above Figure 13-4 shows the result of the following procedure: 1. Enable the auto re-load function. Set the TCNTBn to 160 (50+110) and the TCMPBn to 110. Set the manual update bit and configure the inverter bit (on/off). The manual update bit sets TCNTn and TCMPn to the values of TCNTBn and TCMPBn, respectively.
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PWM TIMER S3C2450X RISC MICROPROCESSOR 2.6 PULSE WIDTH MODULATION (PWM) 60 Write TCMPBn = 60 50 40 Write TCMPBn = 40 Write TCMPBn = 50 30 30 Write TCMPBn = 30 Write TCMPBn = 30 Write TCMPBn = Next PWM Value Figure 13-5. Example of PWM PWM function can be implemented by using the TCMPBn. PWM frequency is determined by TCNTBn. Figure 135 shows a PWM value determined by TCMPBn. For a higher PWM value, decrease the TCMPBn value. For a lower PWM value, increase the TCMPBn value.
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S3C2450X RISC MICROPROCESSOR PWM TIMER 2.7 OUTPUT LEVEL CONTROL Inverter off Inverter on Initial State Period 1 Period 2 Timer Stop Figure 13-6. Inverter On/Off The following procedure describes how to maintain TOUT as high or low (assume the inverter is off): 1. Turn off the auto reload bit. And then, the timer is stopped after the TCNTn reaches 0, TOUTn goes to high level (recommended). 2. Stop the timer by clearing the timer start/stop bit to 0.
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PWM TIMER S3C2450X RISC MICROPROCESSOR 2.8 DEAD ZONE GENERATOR The Dead Zone is for the PWM control in a power device. This function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device. This time gap prohibits the two switching devices from being turned on simultaneously, even for a very short time. TOUT0 is the PWM output. nTOUT0 is the inversion of the TOUT0.
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S3C2450X RISC MICROPROCESSOR PWM TIMER 2.9 DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time. The timer keeps DMA request signals (nDMA_REQ) low until the timer receives an ACK signal. When the timer receives the ACK signal, it makes the request signal inactive. The timer, which generates the DMA request, is determined by setting DMA mode bits (in TCFG1 register). If one of timers is configured as DMA request mode, that timer does not generate an interrupt request.
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PWM TIMER S3C2450X RISC MICROPROCESSOR 3 PWM TIMER CONTROL REGISTERS 3.1 TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 Register Address R/W TCFG0 0x51000000 R/W TCFG0 Bit Description Configures the two 8-bit prescalers Description Reset Value 0x00000000 Initial State Reserved [31:24] Dead zone length [23:16] These 8 bits determine the dead zone length.
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S3C2450X RISC MICROPROCESSOR PWM TIMER 3.2 TIMER CONFIGURATION REGISTER1 (TCFG1) Register Address R/W TCFG1 0x51000004 R/W TCFG1 Bit Description 5-MUX & DMA mode selection register Description Reset Value 0x00000000 Initial State Reserved [31:24] 00000000 DMA mode [23:20] Select DMA request channel 0000 = No select (all interrupt) 0001 = Timer0 0010 = Timer1 0011 = Timer2 0100 = Timer3 0101 = Timer4 0110 = Reserved 0000 MUX 4 [19:16] Select MUX input for PWM Timer4.
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PWM TIMER S3C2450X RISC MICROPROCESSOR 3.3 TIMER CONTROL (TCON) REGISTER Register Address R/W TCON 0x51000008 R/W TCON Description Timer control register Bit Description Reset Value 0x00000000 Initial state Timer 4 auto reload on/off [22] Determine auto reload on/off for Timer 4. 0 = One-shot 1 = Interval mode (auto reload) 0 Timer 4 manual update (note) [21] Determine the manual update for Timer 4.
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S3C2450X RISC MICROPROCESSOR TCON Reserved PWM TIMER Bit [7:5] Description Initial state Reserved Dead zone enable [4] Determine the dead zone operation. 0 = Disable 1 = Enable 0 Timer 0 auto reload on/off [3] Determine auto reload on/off for Timer 0. 0 = One-shot 1 = Interval mode(auto reload) 0 Timer 0 output inverter on/off [2] Determine the output inverter on/off for Timer 0.
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PWM TIMER S3C2450X RISC MICROPROCESSOR 3.
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S3C2450X RISC MICROPROCESSOR PWM TIMER 3.
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PWM TIMER S3C2450X RISC MICROPROCESSOR 3.
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S3C2450X RISC MICROPROCESSOR PWM TIMER 3.
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PWM TIMER S3C2450X RISC MICROPROCESSOR 3.12 TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register Address R/W TCNTB4 0x5100003C R/W TCNTB4 Description Timer 4 count buffer register Bit Timer 4 count buffer register [15:0] Description Set count buffer value for Timer 4 Reset Value 0x00000000 Initial State 0x00000000 3.
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S3C2450X RISC MICROPROCESSOR 14 REAL TIME CLOCK REAL TIME CLOCK (RTC) This chapter describes the functions and usage of Real Time Clock (RTC) in S3C2450 RISC microprocessor. 1 OVERVIEW The Real Time Clock (RTC) unit can be operated by the backup battery when the system power is off. The data include the time by second, minute, hour, date, day, month, and year. The RTC unit works with an external 32.768 KHz crystal and can perform the alarm function. 1.
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REAL TIME CLOCK S3C2450X RISC MICROPROCESSOR 1.2 REAL TIME CLOCK OPERATION DESCRIPTION TI CNT TI CWKUP Ti me Ti ck Gener at or 32KHz~1Hz 215 Cl ock Di vi der TI CI NT RTCRST Reset Regi st er Leap Year Gener at or XTI r t c 1 Hz SEC MI N HOUR DATE DAY MON YEAR XTOr t c Cont r ol Regi st er Al ar m Gener at or RTCCON RTCALM ALMWKUP ALMI NT Figure 14-1. Real Time Clock Block Diagram 1.2.
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S3C2450X RISC MICROPROCESSOR REAL TIME CLOCK 1.2.2 Read/Write Register Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block. To display the second, minute, hour, day, date, month, and year, the CPU must read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDATE, BCDDAY, BCDMON, and BCDYEAR registers respectively in the RTC block. However, a one second deviation may exist because multiple registers are read.
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REAL TIME CLOCK S3C2450X RISC MICROPROCESSOR 1.2.5 Tick time interrupt The RTC tick time is used for interrupt request. The TICNT register has an interrupt enable bit and the count value for the interrupt. The count value reaches ‘0’ when the tick time interrupt occurs.
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S3C2450X RISC MICROPROCESSOR REAL TIME CLOCK Figure 14-2. RTC Tick Interrupt Clock Scheme Example) For 1 ms Tick interrupt generation. 1st ) RTCCON[0]= 1’b1 ( RTC enable ) 2nd) RTCCON[3]=1’b1 ( RTC clock counter reset). 3rd) RTCCON[3] = 1’b0 ( RTC clock counter enable) 4th) RTCCON[8:5] = 4’b0011 ( RTC divide clock selection.) 5th) TICNT1[6:0] = 7’h1 (Tick counter value setting). 6th) TICNT0[7] = 1’b1 (Tick counter enable).
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REAL TIME CLOCK S3C2450X RISC MICROPROCESSOR 1.2.6 32.768 kHz X-TAL Connection EXAMPLE The Figure 14-3 shows a circuit of the RTC unit oscillation at 32.768 kHz. VDD_RTC 15~22pF 32768Hz XTIRTC XTIRTC XTORTC XTORTC 5Mohm 15~22pF A) RTC Block is used B) RTC Block is not used Figure 14-3. Main Oscillator Circuit Example 1.
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S3C2450X RISC MICROPROCESSOR REAL TIME CLOCK 1.4 REGISTER DESCRIPTION 1.4.1 Memory Map Table 14-1.
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REAL TIME CLOCK S3C2450X RISC MICROPROCESSOR 1.5 INDIVIDUAL REGISTER DESCRIPTIONS 1.5.1 REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 9 bits. It controls the read/write enable of the CLKSEL, CNTSEL and CLKRST for testing. RTCEN bit can control all interfaces between the CPU and the RTC, Therefore it must be set to 1 in an RTC control routine to enable data read/write after a system reset.
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S3C2450X RISC MICROPROCESSOR REAL TIME CLOCK 1.5.2 Tick Time Count Register 0 (TICNT0) The TICNT0 register determines tick interrupt enable and tick counter value S3C2450 supports 32bits tic time counter. So, from 14 to 8bits of 32bit tick time count value is selected at TICNT0 register (TICNT0[6:0]). Lower 8bits of 15bit tick time count value is selected at TICNT1 register (TICNT1[7:0]). Upper 17 bits of 32bit tick time count value is selected at TICNT2 register (TICNT0[16:0]).
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REAL TIME CLOCK S3C2450X RISC MICROPROCESSOR 1.5.4 Tick Time Count Register 2 (TICNT2) Register Address R/W TICNT2 0x57000048 R/W TICNT2 Bit TICK TIME COUNT 2 [16:0] Description Tick time count register 2 Description High 17 bits of 32bit tick time count value Reset Value 0x00 Initial State b’000000 1.5.5 RTC ALARM Control (RTCALM) Register The RTCALM register determines the alarm enable and the alarm time.
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S3C2450X RISC MICROPROCESSOR REAL TIME CLOCK 1.5.6 ALARM Second Data (ALMSEC) Register Register Address R/W ALMSEC 0x57000054 R/W ALMSEC Description Alarm second data Register Bit Description Reset Value 0x0 Initial State Reserved [7] 0 SECDATA [6:4] BCD value for alarm second. 0~5 000 [3:0] 0~9 0000 1.5.
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REAL TIME CLOCK S3C2450X RISC MICROPROCESSOR 1.5.9 ALARM DATE Data (ALMDATE) Register Register Address R/W ALMDATE 0x57000060 R/W ALMDATE Description Reset Value Alarm day data Register 0x01 Description Initial State Bit Reserved [7:6] 00 DATEDATA [5:4] BCD value for alarm date, from 0 to 28, 29, 30, 31. 0~3 [3:0] 0~9 00 0001 1.5.
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S3C2450X RISC MICROPROCESSOR REAL TIME CLOCK 1.5.12 BCD SECOND (BCDSEC) Register Register Address R/W BCDSEC 0x57000070 R/W BCDSEC SECDATA Description BCD second Register Bit Description Reset Value Undefined Initial State [6:4] BCD value for second. 0~5 − [3:0] 0~9 − 1.5.13 BCD MINUTE (BCDMIN) Register Register Address R/W BCDMIN 0x57000074 R/W BCDMIN MINDATA Description BCD minute Register Bit Description Reset Value Undefined Initial State [6:4] BCD value for minute.
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REAL TIME CLOCK S3C2450X RISC MICROPROCESSOR 1.5.15 BCD DATE (BCDDATE) Register Register Address R/W BCDDATE 0x5700007C R/W BCDDAY Description BCD DATE Register Bit Description Reset Value Undefined Initial State − Reserved [7:6] DATEDATA [5:4] BCD value for date. 0~3 − [3:0] 0~9 − 1.5.
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S3C2450X RISC MICROPROCESSOR REAL TIME CLOCK 1.5.18 BCD YEAR (BCDYEAR) Register Register Address R/W BCDYEAR 0x57000088 R/W BCDYEAR Description BCD year Register Bit YEARDATA Description [7:4] BCD value for year. Reset Value Undefined Initial State 0x0 0~9 [3:0] 0~9 0x0 NOTE: For setting BCD registers, RTCEN(RTCCON[0] bit) must be ebable. But at no setting BCD registers, RTCEN must be disable for reducing power comsumption. 1.5.
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REAL TIME CLOCK S3C2450X RISC MICROPROCESSOR NOTES 14-16
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S3C2450X RISC MICROPROCESSOR 15 UART UART 1 OVERVIEW The S3C2450 Universal Asynchronous Receiver and Transmitter (UART) provide four independent asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. The UART can support bit rates up to 3Mbps bps. Each UART channel contains two 64-byte FIFOs for receiver and transmitter.
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UART S3C2450X RISC MICROPROCESSOR 2 BLOCK DIAGRAM Peripheral BUS Transmitter Transmit FIFO Register (FIFO mode) Transmit Buffer Register(64 Byte) Transmit Holding Register (Non-FIFO mode) Transmit Shifter Control Unit Buad-rate Generator TXDn Clock Source (PCLK, EXTUARTCLK, EPLL clock/n) Receiver RXDn Receive Shifter Receive Buffer Register(64 Byte) Receive Holding Register (Non-FIFO mode only) Receive FIFO Register (FIFO mode) In FIFO mode, all 64 Byte of Buffer register are used as FIFO re
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S3C2450X RISC MICROPROCESSOR UART 2.1 UART OPERATION The following sections describe the UART operations that include data transmission, data reception, auto flow control, interrupt generation, Loopback mode, Infrared mode, and baud-rate generation. 2.1.1 Data Transmission The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn).
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UART S3C2450X RISC MICROPROCESSOR 2.1.3 Auto Flow Control (AFC) UART 0, UART 1 and UART 2 support auto flow control with nRTS and nCTS signals. In AFC, nCTS signals control the operation of the transmitter, and nRTS depends on the condition of the receiver. The UART's transmitter transfers the data in FIFO only when nCTS signals are activated(Low) (In AFC, nCTS means that other UART's FIFO is ready to receive data or not).
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S3C2450X RISC MICROPROCESSOR UART 2.1.4 Non Auto-Flow Control (Controlling nRTS and nCTS by Software) If users want to connect a UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software. Example: Rx Operation with FIFO 1. Select receive mode (Interrupt or DMA mode). 2. Check the value of Rx FIFO count in UFSTATn register.
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UART S3C2450X RISC MICROPROCESSOR 2.1.6 Interrupt/DMA Request Generation Each UART of the S3C2450 has seven status (Tx/Rx/Error) signals: Overrun error, Parity error, Frame error, Break, Receive buffer data ready, Transmit buffer empty, and Transmit shifter empty, all of which are indicated by the corresponding UART status register (UTRSTATn/UERSTATn). The overrun error, parity error, frame error and break condition are referred to as the receive error status.
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S3C2450X RISC MICROPROCESSOR UART 2.1.7 UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out. To clear the error status FIFO, the URXHn with an error and UERSTATn must be read out.
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UART S3C2450X RISC MICROPROCESSOR 2.1.8 Loopback Mode The S3C2450 UART provides a test mode referred to as the Loopback mode, to aid in isolating faults in the communication link. This mode structurally enables the connection of RXD and TXD in the UART. In this mode, therefore, transmitted data is received to the receiver, via RXD. This feature allows the processor to verify the internal transmit and to receive the data path of each SIO channel.
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S3C2450X RISC MICROPROCESSOR UART Figure 15-5. Serial I/O Frame Timing Diagram (Normal UART) Figure 15-6. Infrared Transmit Mode Frame Timing Diagram Figure 15-7.
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UART S3C2450X RISC MICROPROCESSOR 2.1.10 Baud-rate Generation Each UART's baud-rate generator provides the serial clock for the transmitter and the receiver. The source clock for the baud-rate generator can be selected with the S3C2450's internal system clock(PCLK or divided EPLL clock) or EXTUARTCLK. UARTCLK (Clock frequencies of 16 times the baud rate) are used for sampling serial data to minimize error. UARTCLK is generated by dividing the source clock.
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S3C2450X RISC MICROPROCESSOR UART 2.1.11 Baud-Rate Error Tolerance UART Frame error should be less than 1.87%(3/160).
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UART S3C2450X RISC MICROPROCESSOR 3 UART SPECIAL REGISTERS 3.1 UART LINE CONTROL REGISTER There are four UART line control registers including ULCON0, ULCON1, ULCON2 and ULCON3 in the UART block.
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S3C2450X RISC MICROPROCESSOR UART 3.2 UART CONTROL REGISTER There are four UART control registers including UCON0, UCON1, UCON2 and UCON3 in the UART block.
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UART S3C2450X RISC MICROPROCESSOR UCONn Transmit Mode Bit [3:2] (note 3) Description Determine which function is currently able to write Tx data to the UART transmit buffer register. Initial State 00 00 = Disable 01 = Interrupt request (note 6) or polling mode 10 = DMA request( request signal 0) 11 = DMA request( request signal 1) Receive Mode [1:0] Determine which function is currently able to read data from UART receive buffer register.
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S3C2450X RISC MICROPROCESSOR UART 3.3 UART FIFO CONTROL REGISTER There are four UART FIFO control registers including UFCON0, UFCON1, UFCON2 and UFCON3 in the UART block.
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UART S3C2450X RISC MICROPROCESSOR 3.4 UART MODEM CONTROL REGISTER There are three UART MODEM control registers including UMCON0 and UMCON1 in the UART block.
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S3C2450X RISC MICROPROCESSOR UART 3.5 UART TX/RX STATUS REGISTER There are four UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1, UTRSTAT2 and UTRSTAT3 in the UART block.
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UART S3C2450X RISC MICROPROCESSOR 3.6 UART ERROR STATUS REGISTER There are four UART Rx error status registers including UERSTAT0, UERSTAT1, UERSTAT2 and UERSTAT3 in the UART block.
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S3C2450X RISC MICROPROCESSOR UART 3.7 UART FIFO STATUS REGISTER There are four UART FIFO status registers including UFSTAT0, UFSTAT1 UFSTAT2 and UFSTAT3 in the UART block.
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UART S3C2450X RISC MICROPROCESSOR 3.8 UART MODEM STATUS REGISTER There are three UART modem status registers including UMSTAT0, UMSTAT1 in the UART block.
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S3C2450X RISC MICROPROCESSOR UART 3.9 UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are four UART transmit buffer registers including UTXH0, UTXH1, UTXH2 and UTXH3 in the UART block. UTXHn has an 8-bit data for transmission data.
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UART S3C2450X RISC MICROPROCESSOR 3.11 UART BAUD RATE DIVISOR REGISTER There are four UART baud rate divisor registers including UBRDIV0, UBRDIV1, UBRDIV2 and UBRDIV3 in the UART block.
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S3C2450X RISC MICROPROCESSOR UART 3.12 UART DIVIDING SLOT REGISTER There are four UART dividing slot registers including UDIVSLOT0, UDIVSLOT 1, UDIVSLOT 2 and UDIVSLOT in the UART block.
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UART S3C2450X RISC MICROPROCESSOR NOTES 15-24
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S3C2450X RISC MICROPROCESSOR 16 USB HOST CONTROLLER USB HOST CONTROLLER 1 OVERVIEW S3C2450 supports 2-port USB host interface as follows: • OHCI Rev 1.0 compatible • USB Rev1.
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USB HOST CONTROLLER S3C2450X RISC MICROPROCESSOR 1.1 USB HOST CONTROLLER SPECIAL REGISTERS The S3C2450 USB host controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.0 specification for detail information. Table 16-1.
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S3C2450X RISC MICROPROCESSOR 17 USB2.0 DEVICE USB 2.0 FUNCTION 1 OVERVIEW The Samsung USB 2.0 Controller is designed to aid the rapid implementation of the USB 2.0 peripheral device. The controller supports both High and Full speed mode. Using the standard UTMI interface and AHB interface the USB 2.0 Controller can support up to 9 Endpoints (including Endpoint0) with programmable Interrupt, Bulk mode. 1.1 FEATURE • Compliant to USB 2.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 2 BLOCK DIAGRAM System Controller SFR setting Internal Clock (48Mhz) PHY Clock (30Mhz) AHB Master/Slave Interface USB 2.0 PHY Control Block USB 2.0 Function PHY Clock (48Mhz or 30Mhz) PHY Control Signal DP UTMI Interface Serial Interface USB 2.0 PHY DM AHB Master/Slave Interface External USB HOST or Device USB 1.1 Host PHY or Internal Clock (48Mhz) Serial Interface 2 USB 1.1 Transceiver DP DN Figure 17-1. USB2.0 Block Diagram USB2.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 3 TO ACTIVATE USB PORT1 FOR USB 2.0 FUNCTION USB Function block of S3C2450 shares USB PORT1 with USB Host block. To activate USB PORT1 for USB Function, see USB control registers in System Controller Guide AHB Slave Interface UTMI Interface UPH SIE UTMI AHB Master Interface FIFO BLOCK Figure 17-2. USB2.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 4 SIE (SERIAL INTERFACE ENGINE) This block handles NRZI decoding/encoding, CRC generation and checking, and bit-stuffing. It also provides the interface signals for USB Transceiver. 5 UPH (UNIVERSAL PROTOCOL HANDLER) This block includes state machines and FIFO control, control/status register and DMA control block of each direction endpoint. 6 UTMI (USB 2.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 7 USB 2.0 FUNCTION CONTROLLER SPECIAL REGISTERS The USB 2.0 controller includes several 16-bit registers for the endpoint programming and debugging. The registers can be grouped into two categories. Few of the indexed registers are related to endpoint 0, but most of them are utilized for the control and status monitoring of each data endpoint, including FIFO control and packet size configuration.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR Table 17-2.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8 REGISTERS 8.1 INDEX REGISTER (IR) The index register is used for indexing a specific endpoint. In most cases, setting the index register value should precede any other operation.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.2 ENDPOINT INTERRUPT REGISTER (EIR) The endpoint interrupt register lets the MCU knows what endpoint generates the interrupt. The source of an interrupt could be various, but, when an interrupt is detected, the endpoint status register should be checked to identify if it’s related to specific endpoint. Clearing the bits can be accomplished by writing “1” to the bit position where the interrupt is detected.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.3 ENDPOINT INTERRUPT ENABLE REGISTER (EIER) Pairing with interrupt register, this register enables interrupt for each endpoints.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.4 FUNCTION ADDRESS REGISTER (FAR) This register holds the address of USB device. Register Address R/W FAR 0x4980_000C R FAR FA 17-10 Bit R/W [31:7] [6:0] Description Function address register Reset Value 0x0 Description Initial State − Reserved R MCU can read a unique USB function address from this register. The address is transferred from USB Host through “set_address” command.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.5 ENDPOINT DIRECTION REGISTER (EDR) USB 2.0 Core supports IN/OUT direction control for each endpoint. This direction can’t be changed dynamically. Only by new enumeration, the direction can be altered. Since the endpoint 0 is bi-directional, there is no direction bit assigned to it.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.6 TEST REGISTER (TR) The test register is used for the diagnostics. All bit are activated when 1 is written to and is cleared by 0 on them. Bit[3:0] are for the high speed device only. Register Address R/W TR 0x4980_0018 R/W TR TMD Bit R/W [31:5] − [4] R/W Description Test register Reset Value 0x0 Description Initial State Reserved Test Mode. 0 When TMD is set to 1. The core is forced into the test mode.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.7 SYSTEM STATUS REGISTER (SSR) This register reports operational status of the USB 2.0 Function Core, especially about error status and power saving mode status. Except the line status, every status bits in the System Status Register could be an interrupt sources. When the register is read after an interrupt due to certain system status changes, MCU should write back 1 to the corresponding bits to clear it.
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USB2.0 DEVICE SSR SDE S3C2450X RISC MICROPROCESSOR Bit R/W [3] R/C Description Speed Detection End. Initial State 0 SDE is set by the core when the HS Detect Handshake process is ended. HFRM [2] R/C Host Forced Resume. 0 HFRM is set by the core in suspend state when host sends resume signaling. HFSUSP [1] R/C Host Forced Suspend 0 HFSUSP is set by the core when the SUSPEND signaling from host is detected. HFRES [0] R/C Host Forced Reset.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.8 SYSTEM CONTROL REGISTER (SCR) This register enables top-level control of the core. MCU should access this register for controls such as Power saving mode enable/disable.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.9 EP0 STATUS REGISTER (EP0SR) This register stores status information of the Endpoint 0. These status information are set automatically by the core when corresponding conditions are met. After reading the bits, MCU should write 1 to clear them.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.10 EP0 CONTROL REGISTER (EP0CR) EP0 control register is used for the control of endpoint 0. Controls such as enabling ep0 related interrupts and toggle controls can be handled by EP0 control register.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.11 ENDPOINT# BUFFER REGISTER (EP#BR) The buffer register is used to hold data for TX/RX transfer.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.12 ENDPOINT STATUS REGISTER (ESR) The endpoint status register reports current status of an endpoint (except EP0) to the MCU Register Address R/W ESR 0x4980_002C R/W ESR Bit [11] Endpoint status register R/W [31:12] FPID Description Description Reset Value 0x0 Initial State Reserved R/W First OUT Packet interrupt Disable in OUT DMA operation.
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USB2.0 DEVICE ESR PSIF S3C2450X RISC MICROPROCESSOR Bit R/W [3:2] R Description Packet Status In FIFO. Initial State 0 00 = No packet in FIFO 01 = One packet in FIFO 10 = Two packet in FIFO 11 = Invalid value TPS [1] R/C Tx Packet Success 0 TPS is used for Single or Dual transfer mode. TPS is activated when one packet data in FIFO was successfully transferred to Host and received ACK from Host. This bit should be cleared by writing 1 on it after being read by the MCU.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.13 ENDPOINT CONTROL REGISTER (ECR) The endpoint control register is useful for controlling an endpoint both in normal operation and test case. Putting an endpoint in specific operation mode can be accomplished through the endpoint control register.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.14 BYTE READ COUNT REGISTER (BRCR) The byte read count register keeps byte (half word) counts of a RX packet from USB host. Register Address R/W BRCR 0x4980_0034 R BRCR RDCNT Bit R/W [31:10] [9:0] Description Byte Read Count Register 0x0 Description Initial State − Reserved R FIFO Read Byte Count[9:0] RDCNT is read only. The BRCR inform the amount of received data from host.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.15 BYTE WRITE COUNT REGISTER (BWCR) The byte write count register keeps the byte (half word) count value of a TX packet from MCU. The counter value will be used to determine the end of TX packet. Register Address R/W BWCR 0x4980_0038 R/W BWCR WRCNT Bit R/W [31:10] − [9:0] R/W Description Byte Write Count Register Reset Value 0x0 Description Initial State Through BWCR, the MCU must load the byte counts of a TX data packet to the core.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.16 MAX PACKET REGISTER (MPR) The byte write count register keeps the byte (half word) count value of a TX packet from MCU. The counter value will be used to determine the end of TX packet. Register MPR MPR MAXP Address R/W 0x4980_003C R/W Bit R/W [31:11] − [10:0] R/W Description MAX Packet Register Description 0x0 Initial State Reserved MAX Packet [10:0] The max packet size of each endpoint is determined by MAX packet register.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.17 DMA CONTROL REGISTER (DCR) The AHB Master Operation is controlled by the programming DMA Control Register and DMA IF Control Register. Register Address R/W DCR 0x4980_0040 R/W DCR ARDRD Bit R/W [31:6] − [5] R/W Description DMA Control Register Description Reset Value 0x0 Initial State Reserved Auto Rx DMA Run set disable. 0 0 = Set 1 = Disable This bit is cleared when DMA operation is ended. FMDE [4] R/W Burst Mode Enable.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.18 DMA TRANSFER COUNTER REGISTER (DTCR) The byte write count register keeps the byte (half word) count value of a TX packet from MCU. The counter value will be used to determine the end of TX packet. Register Address R/W Description DTCR 0x4980_0044 R/W DMA Transfer Counter Register MTCR Bit R/W [31:11] DTCR 17-26 [10:0] Reset Value 0x0 Description Initial State To operate single mode transfer, DTCR is needed to be set 11’h0002.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.19 DMA FIFO COUNTER REGISTER (DFCR) This register has the byte number of data per DMA operation. The max packet size is loaded in this register. Register Address R/W DFCR 0x4980_0048 R/W MFCR DFCR Bit R/W [31:12] − [11:0] R/W Description DMA FIFO Counter Register Description Reset Value 0x0 Initial State Reserved In case of OUT Endpoint, the size value of received packet will be loaded in this register automatically when Rx DMA Run is enabled.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.20 DMA TOTAL TRANSFER COUNTER REGISTER 1/2 (DTTCR 1/2) This register has the total byte number of data to transfer using DMA Interface. When this counter register value is zero, DMA operation is ended.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.21 DMA INTERFACE CONTROL REGISTER (DICR) The AHB Master Operation is controlled by the programming DMA Control Register and DMA IF Control Register.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.22 MEMORY BASE ADDRESS REGISTER (MBAR) Register Address R/W Description MBAR 0x4980_0088 R/W Memory Base Address Register MBAR# MBAR 17-30 Bit R/W [31:0] R/W Description This register should have memory base address to be transferred using DMA Interface.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.23 MEMORY CURRENT ADDRESS REGISTER (MCAR) Register Address R/W MCAR 0x4980_008C R MCAR# MCAR Bit R/W [31:0] R Description Memory Current Address Register Description Reset Value 0x0 Initial State This register should have memory current address to be transferred using DMA Interface. 8.
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USB2.0 DEVICE S3C2450X RISC MICROPROCESSOR 8.26 AHB MASTER(DMA) OPERATION FLOW CHART 8.26.1 A. OUT Transfer Operation Flow AHB Master IF Registers (Unit Counter, Total Transfer Counter, Control) are set in initial state or Interrupt service routine. AHB Master IF Registers are to be set after MCU reads all data packets from USB OUT FIFO to operate a AHB Master operation after interrupt service mode. USB Core receives OUT data from HOST PC and transfers to Memory.
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S3C2450X RISC MICROPROCESSOR USB2.0 DEVICE 8.26.2 B. IN Transfer Operation Flow AHB Master Registers( Unit Counter, Total Transfer Counter, Control) are set in intial state or Interrupt service routine. AHB Master Registers are to be set after MCU writes one packet data to USB IN FIFO to operate a AHB Master operation after interrupt service mode USB Core receives IN TOKEN from Host PC and sends IN data to HOST PC.
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USB2.
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S3C2450X RISC MICROPROCESSOR 18 IIC-BUS INTERFACE IIC-BUS INTERFACE 1 OVERVIEW The S3C2450 RISC microprocessor can support two channels of multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus. The SDA and SCL lines are bi-directional.
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IIC-BUS INTERFACE S3C2450X RISC MICROPROCESSOR Address Register Comparator IIC-Bus Control Logic SCL PCLK IICCON IICSTAT 4-bit Prescaler Shift Register Shift Register (IICDS) Data Bus Figure 18-1.
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S3C2450X RISC MICROPROCESSOR IIC-BUS INTERFACE 1.1 IIC-BUS INTERFACE The S3C2450 IIC-bus interface has four operation modes: • Master transmitter mode • Master receive mode • Slave transmitter mode • Slave receive mode Functional relationships among these operating modes are described below. 1.2 START AND STOP CONDITIONS When the IIC-bus interface is inactive, it is usually in Slave mode.
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IIC-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 1.3 DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode. Each byte should be followed by an acknowledgement (ACK) bit. The MSB bit of the serial data and addresses are always sent first.
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S3C2450X RISC MICROPROCESSOR IIC-BUS INTERFACE SDA Acknowledgement Signal from Receiver MSB 2 1 SCL 7 8 S 9 Acknowledgement Signal from Receiver 1 2 9 ACK Byte Complete, Interrupt within Receiver Clock Line Held Low by receiver and/or transmitter Figure 18-4. Data Transfer on the IIC-Bus 1.4 ACK SIGNAL TRANSMISSION To complete a one-byte transfer operation, the receiver should send an ACK bit to the transmitter. The ACK pulse should occur at the ninth clock of the SCL line.
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IIC-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 1.5 READ-WRITE OPERATION In Transmitter mode, when the data is transferred, the IIC-bus interface will wait until IIC-bus Data Shift (IICDS) register receives a new data. Before the new data is written into the register, the SCL line will be held low, and then released after it is written. The S3C2450 should hold the interrupt to identify the completion of current data transfer.
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S3C2450X RISC MICROPROCESSOR IIC-BUS INTERFACE 1.9 FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1. Write own slave address on IICADD register, if needed. 2. Set IICCON register. a) Enable interrupt b) Define SCL period 3. Set IICSTAT to enable Serial Output START Master Tx mode has been configured. Write slave address to IICDS. Write 0xF0 (M/T Start) to IICSTAT. The data of the IICDS is transmitted.
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IIC-BUS INTERFACE S3C2450X RISC MICROPROCESSOR START Master Rx mode has been configured. Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Stop? Y N Read a new data from IICDS. Write 0x90 (M/R Stop) to IICSTAT. Clear pending bit to resume. Clear pending bit . SDA is shifted to IICDS. Wait until the stop condition takes effect. END Figure 18-7.
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S3C2450X RISC MICROPROCESSOR IIC-BUS INTERFACE START Slave Tx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? N Y The IIC address match interrupt is generated. Write data to IICDS. Clear pending bit to resume. Stop? Y N The data of the IICDS is shifted to SDA. END Interrupt is pending. Figure 18-8.
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IIC-BUS INTERFACE S3C2450X RISC MICROPROCESSOR START Slave Rx mode has been configured. IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Matched? N Y The IIC address match interrupt is generated. Read data from IICDS. Clear pending bit to resume. Stop? Y N SDA is shifted to IICDS. END Interrupt is pending. Figure 18-9.
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S3C2450X RISC MICROPROCESSOR IIC-BUS INTERFACE 2 IIC-BUS INTERFACE SPECIAL REGISTERS 2.1 MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register Address R/W IICCON0 0x54000000 R/W IIC0-Bus control register 0x0X IICCON1 0x54000100 R/W IIC1-Bus control register 0x0X IICCON0 IICCON1 Acknowledge generation Description Bit [7] (note 1) Description IIC-bus acknowledge enable bit. 0 = Disable 1 = Enable Reset Value Initial State 0 In Tx mode, the IICSDA is free in the ack time.
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IIC-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 2.2 MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register Address R/W IICSTAT0 0x54000004 R/W IIC0-Bus control/status register 0x0 IICSTAT1 0x54000104 R/W IIC1-Bus control/status register 0x0 IICSTAT0 IICSTAT1 Mode selection Description Bit [7:6] Description IIC-bus master/slave Tx/Rx mode select bits.
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S3C2450X RISC MICROPROCESSOR IIC-BUS INTERFACE 2.3 MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register Address R/W IICADD0 0x54000008 R/W IIC0-Bus address register 0xXX IICADD1 0x54000108 R/W IIC1-Bus address register 0xXX IICADD0 IICADD1 Bit Description Initial State [7:0] 7-bit slave address, latched from the IIC-bus. When serial output enable = 0 in the IICSTAT, IICADD is writeenabled.
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IIC-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 2.5 MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTER Register Address R/W IICLC0 0x54000010 R/W IIC0-Bus multi-master line control register 0x00 IICLC1 0x54000110 R/W IIC1-Bus multi-master line control register 0x00 IICLC0 IICLC1 Bit Filter enable [2] Description Description IIC-bus filter enable bit. When SDA port is operating as input, this bit should be High.
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S3C2450X RISC MICROPROCESSOR 19 2D 2D 1 INTRODUCTION 2D graphics accelerator supports three types of primitive drawings: Line/Point Drawing, Bit Block Transfer (BitBLT) and Color Expansion (Text Drawing). Rendering a primitive takes two steps: 1) configure the rendering parameters, such as foreground color and the coordinate data, by setting the drawing-context registers; 2) start the rendering process by setting the relevant command registers accordingly. 1.1 FEATURES 1.1.1 Primitives 1.1.
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2D S3C2450X RISC MICROPROCESSOR 2 COLOR FORMAT CONVERSION 2D supports seven color formats: RGB_565, RGBA_5551, ARGB_1555, RGBA_8888, ARGB_8888, XRGB_8888, and RGBX_8888. The structure of each color format is illustrated in Figure 19-1.
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S3C2450X RISC MICROPROCESSOR YUV422 2-Planar 2D Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y U V U V U V U V U V U V U V U V Figure 19-2. YUV 2-Planar Format 3 COMMAND FIFO 2D has a 32-word command FIFO. Every data written to command registers and parameter setting registers will be written to the FIFO first.
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2D S3C2450X RISC MICROPROCESSOR 4 RENDERING PIPELINE The rendering pipeline of 2D is illustrated in Figure 19-3. The functionality and related registers of each stage are introduced in detail in the rest of this chapter. Figure 19-3. 2D Rendering Pipeline 4.1 PRIMITIVE DRAWING Primitive Drawing determines the pixels to fill, and pass their coordinates to the next stage for further operations. 2D supports three types of primitive drawing: 1) line/point drawing; 2) bit block transfer; 3) color expansion.
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S3C2450X RISC MICROPROCESSOR 2D 4.1.2 Related Registers COORD_0 Coordinate of the starting point COORD_2 Coordinate of the ending point (ignored if a point is rendered). X-INCR X increment value ( ignored if x-axis is the Major Axis or a point is rendered). X-INCR = (ex-sx)/ |ey - sy| Y-INCR Y increment value (ignored if y-axis is the Major Axis or a point is rendered).
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2D S3C2450X RISC MICROPROCESSOR 4.1.6 Transparent Mode 2D can render image in Transparent Mode. In this mode, the pixels having the same color with background color (BG_COLOR) are discarded, resulting in a transparent effect. The function of Transparent Mode is illustrated in the images below, in which the BG_COLOR is set to white. Figure 19-5. Transparent Mode 2D supports both host-to-screen mode and memory-to-screen mode of BLT. 4.1.
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S3C2450X RISC MICROPROCESSOR 2D 4.1.8 Related Registers COORD_0 Coordinate of the leftmost topmost coordinate of the source image COORD_1 Coordinate of the rightmost bottommost coordinate of the source image COORD_2 Coordinate of the leftmost topmost coordinate of the destination image COORD_3 Coordinate of the rightmost bottommost coordinate of the destination image X-INCR X increment value of the source image coordinates.
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2D S3C2450X RISC MICROPROCESSOR 4.1.9 Color Expansion (Font Drawing) Color Expansion expands the monochrome color to either background (BG_COLOR) or foreground (FG_COLOR) color. Each bit of the source data presents a pixel, with ‘1’ indicating the foreground color and ‘0’ the background color. The bit sequence is from MSB to LSB. The MSB of the first data corresponds to the leftmost topmost pixel of the destination image.
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S3C2450X RISC MICROPROCESSOR 2D 4.1.10 Related Registers COORD_0 Coordinate of the leftmost topmost coordinate of the destination window COORD_1 Coordinate of the rightmost bottommost coordinate of the destination window FG_COLOR Foreground Color BG_COLOR Background Color ROP_REG Enable/disable Transparent Mode CMD7_REG The base address of the font data. Note that writing to this register starts the rendering process in the memory-to-screen mode.
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2D S3C2450X RISC MICROPROCESSOR 4.2.2 Rotation Effect 0° 90° 180° 270° X-flip Y-flip x dcx -dcy + (ox+oy) -dcx + 2ox dcy + (ox-oy) dcx -dcx + 2ox y dcy dcx - (ox-oy) -dcy + 2oy -dcx + (ox+oy) -dcy + 2oy dcy Original image 90 ° 180 ° FIMG - 2D 270 ° X - axis flip Figure 19-8.
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S3C2450X RISC MICROPROCESSOR 2D 4.3 CLIPPING Clipping discards the pixels (after rotation) outside the clipping window. The discarded pixels will not go through the rest of rendering pipelines. Note that the clipping windows must reside totally inside the screen. Setting the clipping window the same size with the screen will disable the clipping effect, and a clipping window bigger than the screen size is not allowed. 4.3.
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2D S3C2450X RISC MICROPROCESSOR The third operand can be pattern or foreground color, configurable by the OS bit in the ROP_REG. Pattern is a user-specified 8x8x16-bpp image; the pattern data should be given in RGB565 format. The following equation is used to calculate the pattern index of pixel (x, y): index = ( ((patternOffsetY + y) & 0x7 )<<3 ) + ((patternOffsetX + x)&0x7), where patternOffsetY and patternOffsetX are the offset value specified in register PATOFF_REG.
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S3C2450X RISC MICROPROCESSOR 2D 4.6 ALPHA BLENDING Alpha Blending combines the source color and the destination color in the frame buffer to get the new destination color. The conventional alpha blending equation is: final data = src * alpha + dest * (1.0 − alpha). 2D uses 8-bit integer to represent the alpha value, with 0 indicating 1/256 and 255 indicating 1.0. The equation of converting 8-bit ALPHA value to the actual fractional alpha value is: alpha = (ALPHA+1) / 256.
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2D S3C2450X RISC MICROPROCESSOR 5 REGISTER DESCRIPTIONS Register General Registers CONTROL_REG INTEN_REG FIFO_INTC_REG INTC_PEND_REG FIFO_STAT_REG Command Registers CMD0_REG CMD1_REG Offset R/W Description 0x0000 0x0004 0x0008 0x000C 0x0010 W R/W R/W R/W R 0x0100 0x0104 W W Command register for Line/Point drawing. Command register for BitBLT.
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S3C2450X RISC MICROPROCESSOR Register COORD1_Y_REG COORD2_REG COORD2_X_REG COORD2_Y_REG COORD3_REG COORD3_X_REG COORD3_Y_REG Offset 0x0318 0x0320 0x0324 0x0328 0x0330 0x0334 0x0338 ROT_OC_REG ROT_OC_X_REG ROT_OC_Y_REG ROTATE_REG 0x0340 0x0344 0x0348 0x034C X_INCR_REG Y_INCR_REG 0x0400 0x0404 ROP_REG ALPHA_REG 0x0410 0x0420 FG_COLOR_REG BG_COLOR_REG BS_COLOR_REG SRC_COLOR_MODE_REG DEST_COLOR_MODE_REG 0x0500 0x0504 0x0508 0x0510 0x0514 PATTERN_REG[0:31] PATOFF_REG PATOFF_X_REG PATOFF_Y_REG 0x0600
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2D S3C2450X RISC MICROPROCESSOR 5.1 GENERAL REGISTERS 5.1.1 Control Register (CONTROL_REG) Register Address R/W CONTROL_REG 0x4D408000 W Field Reserved R Description Control register Bit [31:1] [0] Reset Value 0x0 Description Initial State − 0x0 Software Reset Write to this bit results in a one-cycle reset signal to FIMG2D graphics engine. Every command register and parameter setting register will be assigned the “Reset Value”, and the command FIFO will be cleared. 0x0 5.1.
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S3C2450X RISC MICROPROCESSOR 2D 5.1.3 FIFO Interrupt Control Register (FIFO_INTC_REG) Register Address R/W FIFO_INTC_REG 0x4D408008 R/W Field Description FIFO Interrupt Control Bit Description Reset Value 0x18 Initial State Reserved [31:6] − 0x0 FIFO_INT_LEVEL [5:0] If FIFO_INT_E (in INTEN_REG) is set, when FIFO_USED (in FIFO_STAT_REG) is greater or equal to FIFO_INT_LEVEL, an interrupt occurs. 0x18 5.1.
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2D S3C2450X RISC MICROPROCESSOR 5.1.5 FIFO Statue Register (FIFO_STAT_REG) Register FIFO_STAT_REG Field Address R/W 0x4D408010 R Bit Description FIFO Status Register Description − Reset Value 0x600 Initial State − Reserved [31:11] CMD_FIN [10] 1 = The graphics engine finishes the execution of current command. 0 = In the middle of rendering process. 0x1 ALL_FIN [9] 1 = Graphics engine is in idle state. The graphics engine finishes the execution of all commands in the command FIFO.
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S3C2450X RISC MICROPROCESSOR 2D 5.2 COMMAND REGISTERS 5.2.1 LINE Drawing Register (CMD0_REG) Register Address R/W CMD0_REG 0x4D408100 W Field Reserved Description Line Drawing Register Bit Description [31:10] Reset Value 0x0 Initial State − − D [9] 0 = Draw Last Point 1 = Do-not-Draw Last Point. − M [8] 0 = Major axis is Y. 1 = Major axis is X. − − − Reserved [7:2] L [1] 0 = Nothing. 1 = Line Drawing. − P [0] 0 = Nothing. 1 = Point Drawing. − 5.2.
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2D S3C2450X RISC MICROPROCESSOR 5.2.4 Host to Screen Continue BitBLT Register (CMD3_REG) Register Address R/W CMD3_REG 0x4D40810C W Field Data Description Host to Screen Continue BitBLT Register Reset Value 0x0 Bit Description Initial State [31:0] BitBLT data (Continue) Note that the data written to this register represents only one pixel, regardless of the source color mode. If the source color mode is 16-bpp (e.g., RGB565), the upper 16 bits of the data are ignored. − 5.2.
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S3C2450X RISC MICROPROCESSOR 2D 5.3 PARAMETER SETTING REGISTERS Resolution 5.3.1 Source Image Resolution Register (SRC_RES_REG) Register Address R/W SRC_RES_REG 0x4D408200 R/W Field Description Source Image Resolution Register 0x0 Description Initial State Bit Reserved [31:27] VertRes [26:16] Reserved [15:11] HoriRes [10:0] Reset Value 0x0 Vertical resolution of source image. Range: 1 ~ 2040 0x0 0x0 Horizontal resolution of source image. Range: 1 ~ 2040.
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2D S3C2450X RISC MICROPROCESSOR 5.3.4 Screen Resolution Register (SC_RES_REG) Register SC_RES_REG Field Address R/W 0x4D408210 R/W Bit Description Screen Resolution Register Description Reset Value 0x0 Initial State Reserved [31:27] − 0x0 VertRes [26:16] Vertical resolution of the screen. Range: 1 ~ 2040 0x0 Reserved [15:11] − 0x0 HoriRes [10:0] Horizontal resolution of the screen. Range: 1 ~ 2040 0x0 5.3.
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S3C2450X RISC MICROPROCESSOR 2D Clipping Window 5.3.7 LeftTop Clipping Window Register (CW_LT_REG) Register CW_LT_REG Field Address R/W 0x4D408220 R/W Bit Description Reset Value LeftTop Clipping Window Register 0x0 Description Initial State Reserved [31:27] − 0x0 TopCW_Y [26:16] Top Y Clipping Window Requirement: TopCW_Y < BottomCW_Y 0x0 Reserved [15:11] − 0x0 LeftCW_X [10:0] Left X Coordinate of Clipping Window. Requirement: LeftCW_X < RightCW_X 0x0 5.3.
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2D S3C2450X RISC MICROPROCESSOR 5.3.10 RightBottom Clipping Window Register (CW_RB_REG) Register CW_RB_REG Field Address R/W 0x4D408230 R/W Bit Description RightBottom Clipping Window Register Description Reset Value 0x0 Initial State Reserved [31:27] − 0x0 BottomCW_Y [26:16] Bottom Y Clipping Window Requirement: BottomCW_Y < VeriRes (SC_VERI_RES_REG) 0x0 Reserved [15:11] − 0x0 RightCW_X [10:0] Right X Clipping Window Requirement: RightCW_X < HoriRes (SC_HORI_RES_REG) 0x0 5.3.
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S3C2450X RISC MICROPROCESSOR 2D Coordinates 5.3.13 COORDINATE_0 Register (COORD0_REG) Register COORD0_REG Field Address R/W 0x4D408300 R/W Description Coordinate_0 Register Bit Description Reset Value 0x0 Initial State Reserved [31:27] − 0x0 Y [26:16] Coordinate_0 Y Range: 0 ~ 2039 0x0 Reserved [15:11] − 0x0 X [10:0] Coordinate_0 X Range: 0 ~ 2039 0x0 5.3.
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2D S3C2450X RISC MICROPROCESSOR 5.3.16 COORDINATE_1 Register (COORD1_REG) Register COORD1_REG Field Address R/W 0x4D408310 R/W Description Coordinate_1 Register Bit Description Reset Value 0x0 Initial State Reserved [31:27] − 0x0 Y [26:16] Coordinate_1 Y Range: 0 ~ 2039 0x0 Reserved [15:11] − 0x0 X [10:0] Coordinate_1 X Range: 0 ~ 2039 0x0 5.3.
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S3C2450X RISC MICROPROCESSOR 2D 5.3.19 COORDINATE_2 Register (COORD2 _REG) Register COORD2_REG Field Address R/W 0x4D408320 R/W Description Coordinate_2 Register Bit Description Reset Value 0x0 Initial State Reserved [31:27] − 0x0 Y [26:16] Coordinate_2 Y Range: 0 ~ 2039 0x0 Reserved [15:11] − 0x0 X [10:0] Coordinate_2 X Range: 0 ~ 2039 0x0 5.3.
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2D S3C2450X RISC MICROPROCESSOR 5.3.22 COORDINATE_3 REGISTER (COORD3 _REG) Register COORD3_REG Field Address R/W 0x4D408330 R/W Description Coordinate_3 Register Bit Description Reset Value 0x0 Initial State Reserved [31:27] − 0x0 Y [26:16] Coordinate_3 Y Range: 0 ~ 2039 0x0 Reserved [15:11] − 0x0 X [10:0] Coordinate_3 X Range: 0 ~ 2039 0x0 5.3.
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S3C2450X RISC MICROPROCESSOR 2D Rotation 5.3.25 Rotation Origin Coordinate Register (ROT_OC_REG) Register ROT_OC_REG Field Address R/W 0x4D408340 R/W Bit Description Reset Value Rotation Origin Coordinate Register 0x0 Description Initial State Reserved [31:27] − 0x0 Y [26:16] X coordinate of the reference point of rotation Range: 0 ~ 2039 0x0 Reserved [15:11] − 0x0 X [10:0] Y coordinate of the reference point of rotation Range 0 ~ 2039 0x0 5.3.
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2D S3C2450X RISC MICROPROCESSOR 5.3.28 Rotation Register (ROTATE_REG) Register Address R/W ROTATE_REG 0x4D40834C R/W Field Reserved * Bit Description Rotation Register Description [31:6] Reset Value 0x0 Initial State 0x0 FY [5] Y-flip 0x0 FX [4] X-flip 0x0 R3 [3] 270° Rotation 0x0 R2 [2] 180° Rotation 0x0 R1 [1] 90° Rotation 0x0 R0 [0] 0° Rotation 0x1 If the two or more of Rn are set to 1 at the same time, drawing engine operates unpredictably.
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S3C2450X RISC MICROPROCESSOR 2D X,Y Increment Setting 5.3.29 X Increment Register (X_INCR_REG) Register X_INCR_REG Field Address R/W 0x4D408400 R/W Description X Increment Register Bit Description Reset Value 0x0 Initial State Reserved [31:22] − 0x0 X_INCR [21:0] X increment value (2’s complement, 11-digit fraction) 0x0 5.3.
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2D S3C2450X RISC MICROPROCESSOR ROP & Alpha Setting 5.3.
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S3C2450X RISC MICROPROCESSOR 2D Color 5.3.33 Foreground Color Register (FG_COLOR_REG) Register FG_COLOR_REG Address R/W 0x4D408500 R/W Field Bit ForegroundColor [31:0] Description Foreground Color Register Description Foreground Color Value. The alpha field of the foreground color will be discarded. Reset Value 0x0 Initial State 0x0 5.3.
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2D S3C2450X RISC MICROPROCESSOR 5.3.36 Source Image Color Mode Register (SRC_COLOR_MODE_REG) Register SRC_COLOR_ MODE_REG Field Reserved Address R/W 0x4D408510 R/W Description Source Image Color Mode Register 0x0 Description Initial State Bit [31:5] Reset Value − 0x0 Narrow [4] 1 = YUV narrow range (Y:16-235, UV: 16-240) 0 = YUV wide range (YUV: 0-255) 0x0 YUV [3] 1 = YUV mode 0 = RGB mode This bit should be set to 0 in point/line drawing mode and color expansion mode.
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S3C2450X RISC MICROPROCESSOR 2D Pattern 5.3.38 Pattern Register (PAT_REG) Register PAT_REG Address R/W 0x4D408600 ~ 67C R/W Field PAT_REG Description Pattern Register Bit 0x0 Description [31:0] Reset Value Pattern Register Initial State 0x0 5.3.
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2D S3C2450X RISC MICROPROCESSOR Stencil Test 5.3.42 Colorkey Control Register (COLORKEY_CTRL_REG) Register Address R/W COLORKEY_CTRL _REG 0x4D408720 R/W Field Reserved Description Colorkey Control Register Bit [31:5] Description Reset Value 0x0 Initial State − 0x0 StencilInverse [4] 0 = Normal stencil test 1 = Inversed stencil test This bit should be set to 0 if the stencil test of every color field is disabled.
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S3C2450X RISC MICROPROCESSOR 2D 5.3.44 COLORKEY DECISION REFERENCE MAXIMUM REGISTER (COLORKEY_DR_MAX_REG) Register COLORKEY_DR_ MAX_REG Field Address R/W Description Reset Value 0x4D408728 R/W Colorkey Decision Reference Maximum Register 0xFFFF_FFFF Bit Description Initial State A_DR(max) [31:24] Alpha DR MAX value 0xF R_DR(max) [23:16] RED DR MAX value 0xF G_DR(max) [15:8] GREEN DR MAX value 0xF B_DR(max) [7:0] BLUE DR MAX value 0xF Image Base Address 5.3.
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2D S3C2450X RISC MICROPROCESSOR NOTES 19-38
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S3C2450X RISC MICROPROCESSOR 20 HS_SPI CONTROLLER HS_SPI CONTROLLER 1 OVERVIEW The High Speed Serial Peripheral Interface (HS_SPI) can interface the serial data transfer. HS_SPI has two 8/16/32-bit shift registers for transmission and receiving, respectively. During an HS_SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). HS_SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface.
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HS_SPI CONTROLLER S3C2450X RISC MICROPROCESSOR 3 SIGNAL DESCRIPTIONS The following table lists the external signals between the HS_SPI and external device. All ports of the HS_SPI can be used as General Purpose I/O ports when disable. See “General Purpose I/O” chapter for detailed pin configuration. Table 20-1. External Signals Description Channel Name Direction Description PSPICLK0 Inout PSPICLK0 is the serial clock used to control time to transfer data.
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S3C2450X RISC MICROPROCESSOR HS_SPI CONTROLLER 4.1 OPERATION MODE HS_SPI has 2 modes, master and slave mode. In master mode, SPICLK is generated and transmitted to external device. PSS, which is signal to select slave, indicates data valid when it is low level. PSS should be set low before packets starts to be transmitted or received. 4.2 FIFO ACCESS The HS_SPI in S3C2450 supports CPU access and DMA access to FIFOs. Data size of CPU access and DMA access to FIFOs can be selected 8-bit/16-bit/32-bit data.
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HS_SPI CONTROLLER S3C2450X RISC MICROPROCESSOR 4.6 HS_SPI TRANSFER FORMAT The S3C2450 supports 4 different format to transfer the data. Figure 20-1 shows four waveforms for HS_SPICLK.
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S3C2450X RISC MICROPROCESSOR HS_SPI CONTROLLER 5 SPECIAL FUNCTION REGISTER DESCRIPTIONS 5.1 SETTING SEQUENCE OF SPECIAL FUNCTION REGISTER Special Function Register should be set as the following sequence. (nCS manual mode) 1. Set Transfer Type. (CPOL & CPHA set) 2. Set Clock configuration register. 3. Set HS_SPI MODE configuration register. 4. Set HS_SPI INT_EN register. 5. Set Packet Count configuration register if necessary. 6. Set Tx or Rx Channel on. 7. Set nSSout low to start Tx or Rx operation. A.
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HS_SPI CONTROLLER S3C2450X RISC MICROPROCESSOR 5.2 SPECIAL FUNCTION REGISTER Register Address R/W Description Reset Value CH_CFG(Ch0) 0x52000000 R/W HS_SPI configuration register 0x0000_0040 CH_CFG(Ch1) 0x59000000 R/W HS_SPI configuration register 0x0000_0040 CH_CFG Bit Reserved [31:7] High_speed_en [6] Description Initial State − 26’b0 0 = Low speed operation support at slave mode. 1’b1 1 = High speed operation support at slave mode.
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S3C2450X RISC MICROPROCESSOR HS_SPI CONTROLLER Register Address R/W Clk_CFG(Ch0) 0x52000004 R/W Clock configuration register 0x0 Clk_CFG(Ch1) 0x59000004 R/W Clock configuration register 0x0 Clk_CFG Bit ClkSel [10:9] Description Description Clock source selection to generate HS_SPI clock-out Reset Value Initial State 2’b0 00 = PCLK 01 = USBCLK 10 = Epll clock 11 = Reserved * For using USBCLK source, The USB_SIG_MASK at system controller should be set to on.
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HS_SPI CONTROLLER S3C2450X RISC MICROPROCESSOR Register Address R/W Description MODE_CFG(Ch0) 0x52000008 R/W HS_SPI FIFO control register 0x0 MODE_CFG(Ch1) 0x59000008 R/W HS_SPI FIFO control register 0x0 Description Reset Value MODE_CFG Bit Ch_tran_size [30:29] 00 = Byte 01 = Halfword 10 = Word 11 = Reserved 2’b0 Trailing Count [28:19] Count value from writing the last data in RX FIFO to flush trailing bytes in FIFO 10’b0 BUS transfer size [18:17] 00 = Byte 01 = Halfword 10 = W
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S3C2450X RISC MICROPROCESSOR HS_SPI CONTROLLER Register Address R/W Slave_slection_reg(Ch0) 0x5200000C R/W Slave selection signal 0x1 Slave_slection_reg(Ch1) 0x5900000C R/W Slave selection signal 0x1 Slave_slection_reg Bit nCS_time_count [9:4] reserved [3:2] Auto_n_Manual [1] nSSout [0] Description Description nSSout inactive time = ((nCS_time_count+3)/2) x HS_SPICLKout) Reset Value Initial State 6’b0 − Reserved Chip select toggle manual or auto selection 1’b0 0 = Manual 1 = A
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HS_SPI CONTROLLER S3C2450X RISC MICROPROCESSOR Register Address R/W HS_SPI_STATUS(Ch0 ) 0x52000014 R HS_SPI status register 0x0 HS_SPI_STATUS(Ch1 ) 0x59000014 R HS_SPI status register 0x0 Description Initial State HS_SPI_STATUS Description Bit Reset Value Indication of transfer done in Shift register TX_done [21] 0 = all case except blow case 1 = when tx fifo and shift register are empty 1’b0 * Master mode only Trailing_count_done [20] RxFifoLvl [19:13] TxFifoLvl [12:6] RxOver
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S3C2450X RISC MICROPROCESSOR HS_SPI CONTROLLER Register Address R/W HS_SPI_TX_DATA(Ch0) 0x52000018 W HS_SPI TX DATA register 0x0 HS_SPI_TX_DATA(Ch1) 0x59000018 W HS_SPI TX DATA register 0x0 Description Initial State HS_SPI_TX_DATA Bit TX_DATA [31:0] Description This field contains the data to be transmitted over the HS_SPI channel.
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HS_SPI CONTROLLER S3C2450X RISC MICROPROCESSOR Register Address Pending_clr_reg(Ch0) 0x52000024 R/W Pending clear register 0x0 Pending_clr_reg(Ch1) 0x59000024 R/W Pending clear register 0x0 Status_Pending_ clear_reg R/W Bit Description Description Reset Value Initial State TX underrun pending clear bit TX_underrun_clr [4] 0 = Non-clear 1 = Clear 1’b0 TX overrun pending clear bit TX_overrun_clr [3] RX_underrun_clr [2] RX_overrun_clr [1] Trailing_clr [0] 0 = Non-clear 1 = Clear
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S3C2450X RISC MICROPROCESSOR HS_SPI CONTROLLER Register Address R/W Description SWAP_CFG(Ch0) 0x52000028 R/W SWAP config register 0x0 SWAP_CFG (Ch1) 0x59000028 R/W SWAP config register 0x0 Description Reset Value SWAP_CFG Bit RX_Half-word swap [7] 0 = off 1 = swap 1’b0 RX_Byte swap [6] 0 = off 1 = swap 1’b0 RX_Bit swap [5] 0 = off 1 = swap 1’b0 RX_SWAP_en [4] TX_Half-word swap Swap enable Initial State 1’b0 0 = normal 1 = swap [3] 0 = off 1 = swap 1’b0 TX_Byte sw
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HS_SPI CONTROLLER S3C2450X RISC MICROPROCESSOR NOTES 20-14
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S3C2450X RISC MICROPROCESSOR 21 HSMMC CONTROLLER SD/MMC HOST CONTROLLER This chapter describes the SD/SDIO/MMC/CE-ATA host controller and related registers supported by S3C2450X RISC microprocessor. 1 OVERVIEW The HSMMC (High-speed MMC) SDMMC is a combo host for Secure Digital card and MultiMedia Card. This host is compatible for SD Association’s (SDA) Host Standard Specification. You can interface your system with SD card and MMC card.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 3 BLOCK DIAGRAM BaseCLK SFR INTREQ System Bus (AHB) Clock Control R Status CMD ARG G Control AHB slave I/F DMA controller AHB master CMDRSP packet Line Control Control Pad I/F FIFO Control DPSRAM Control Status DATA packet Figure 21-1.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 4 SEQUENCE This section defines basic sequence flow chart divided into several sub sequences. “Wait for interrupts” is used in the flow chart. This means the Host Driver waits until specified interrupts are asserted. If already asserted, then fall through that step in the flow chart. Timeout checking shall be always required to detect no interrupt generated but this is not described in the flow chart. 4.1 SD CARD DETECTION SEQUENCE Figure 21-2.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 4.2 SD CLOCK SUPPLY SEQUENCE START (1) Calculate a divisor for SD Clock frequency (2) Set SDCLK frequency select and Internal Clock Enable (3) Check Internal Clock Enable (4) Set SD Clock ON End Figure 21-3. SD Clock Supply Sequence The sequence for supplying SD Clock to a SD card is described in Figure 21-3. The clock shall be supplied to the card before either of the following actions is taken.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 4.3 SD CLOCK STOP SEQUENCE START (1) Set SD Clock OFF Stop SD Clock END Figure 21-4. SD Clock Stop Sequence The flow chart for stopping the SD Clock is shown in Figure 21-4. The Host Driver shall not stop the SD Clock when a SD transaction is occurring on the SD Bus -- namely, when either Command Inhibit (DAT) or Command Inhibit (CMD) in the Present State register is set to 1. (1) Set SD Clock Enable(ENSDCLK) in the Clock Control register to 0.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 4.5 SD BUS POWER CONTROL SEQUENCE START (1) Get the support voltage of the Host Controller (2) Set SD Bus voltage select with supported maximum voltage (3) Set SD Bus Power (4) Get OCR value of the SD Card no change (5) SD Bus voltage changed ? (6) change Clr SD Bus Power (7) Set SD Bus voltage select (8) Set SD Bus Power END Figure 21-6. SD Bus Power Control Sequence The sequence for controlling the SD Bus Power is described in Figure 21-6.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 4.6 CHANGE BUS WIDTH SEQUENCE START (1) Disable Card Interrupt in Host (2) SD Memory Only Card ? (3) yes (6) SD Memory Only Card ? no Mask Card Interrupt in Card (7) yes no Enable Card Interrupt in Card (4) Change Bit Mode in Card (8) Enable Card Interrupt in Host (5) Change Bit Mode for Host END Figure 21-7. Change Bus Width Sequence The sequence for changing bit mode on SD Bus is shown in Figure 21-7.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 4.7 TIMEOUT SETTING FOR DAT LINE START (1) Calculate a Divisor for detecting Timeout (2) Set Timeout Detection Timer END Figure 21-8. Timeout Setting Sequence In order to detect timeout errors on DAT line, the Host Driver shall execute the following two steps before any SD transaction. (1) Calculate a divisor to detect timeout errors by reading Timeout Clock Frequency and Timeout Clock Unit in the Capabilities register.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 4.9 SD COMMAND ISSUE SEQUENCE Figure 21-9.
PAGE 508
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR (1) Check Command Inhibit (CMD) in the Present State register. Repeat this step until Command Inhibit (CMD) is 0. That is, when Command Inhibit (CMD) is 1, the Host Driver shall not issue a SD Command. (2) If the Host Driver issues a SD Command with busy signal, go to step (3). If without busy signal, go to step (5). (3) If the Host Driver issues an abort command, go to step (5). In the case of no abort command, go to step (4).
PAGE 509
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER START (1) Wait for Command Complete Int Command Complete Int occur (2) Clr Command Complete Status (3) Get Response Data (4) Command with Transfer Complete Int ? no (5) Wait for Transfer Complete Int Transfer Complete Int occur (6) Clr Transfer Complete Status (7) Check Response Data ? (8) No error Return Status (No Error) Error (9) Return Status (Response Contents Error) END Figure 21-10.
PAGE 510
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 4.11 TRANSACTION CONTROL WITH DATA TRANSFER USING DAT LINE Depending on whether DMA (optional) is used or not, there are two execution methods. The sequence not using DMA is shown in Figure 21-11 and the sequence using DMA is shown in Figure 21-12.
PAGE 511
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER START (1) (5) Set Block Size Reg Set Command Reg (2) (6) Wait for Command Complete Int Set Block Count Reg (3) Command Complete Int occur (7) Set Argument Reg Clr Command Complete Status (4) (8) Set Transfer Mode Reg Get Response Data (9) write read Write or Read ? (10-R) (10-W) Wait for Buffer Write Ready Int (11-W) Wait for Buffer Read Ready Int Buffer Write Ready Int occur (11-R) Clr Buffer Write Ready Status Clr Buffer Read Ready St
PAGE 512
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR (1) Set the value corresponding to the executed data byte length of one block to Block Size register. (2) Set the value corresponding to the executed data block count to Block Count Register. (3) Set the value corresponding to the issued command to Argument register. (4) Set the value to Multi / Single Block Select and Block Count Enable.
PAGE 513
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER START (1) Set System Address Reg (2) Set Block Size Reg (10) Wait for Transfer Complete Int and DMA Int (3) Set Block Count Reg (11) (4) Check Interrupt Status Transfer Complete Int occur Set Argument Reg (5) (12) Set Transfer Mode Reg (6) DMA Int occur Clr DMA Status Interrupt (13) Set Command Reg Set System Address Reg (7) (14) Wait for Command Complete Int (8) Clr Transfer Complete status Clr DMA Interrupt status Command Complete Int occur
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR (10)Wait for the Transfer Complete Interrupt and DMA Interrupt. (11)If Transfer Complete(STATRANCMPLT) is set 1, go to Step (14) else if DMA Interrupt is set to 1, go to Step (12). Transfer Complete is higher priority than DMA Interrupt. (12)Write 1 to the DMA Interrupt in the Normal Interrupt Status register to clear this bit. (13)Set the next system address of the next data position to the System Address register and go to Step (10).
PAGE 515
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5 SDI SPECIAL REGISTERS 5.1 CONFIGURATION REGISTER TYPES Configuration register fields are assigned one of the attributes described below : Register Attribute RO Description Read-only register: Register bits are read-only and cannot be altered by software or any reset operation. Writes to these bits are ignored. ROC Read-only status : These bits are initialized to zero at reset. Writes to these bits are ignored.
PAGE 516
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.2 SDMA SYSTEM ADDRESS REGISTER Register Address R/W Description Reset Value SYSAD0 0X4AC00000 R/W System Address register (Channel 0) 0x0 SYSAD1 0X4A800000 R/W System Address register (Channel 1) 0x0 This register contains the physical system memory address used for DMA transfers. Name Bit SYSAD [31:0] Description SDMA System Address This register contains the system memory address for a DMA transfer.
PAGE 517
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.3 BLOCK SIZE REGISTER This register is used to configure the number of bytes in a data block.
PAGE 518
HSMMC CONTROLLER Name Bit BLKSIZE [11:0] S3C2450X RISC MICROPROCESSOR Description Transfer Block Size This register specifies the block size of data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. Values ranging from 1 up to the maximum buffer size can be set. In case of memory, it shall be set up to 512 bytes. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped).
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.4 BLOCK COUNT REGISTER This register is used to configure the number of data blocks.
PAGE 520
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.5 ARGUMENT REGISTER This register contains the SD Command Argument. Register Address R/W ARGUMENT0 0X4AC00008 R/W Command Argument Register (Channel 0) 0x0 ARGUMENT1 0X4A800008 R/W Command Argument Register (Channel 1) 0x0 Name ARGUMENT Description Bit Description [31:0] Command Argument The SD Command Argument is specified as bit39-8 of CommandFormat in the SD Memory Card Physical Layer Specification.
PAGE 521
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.6 TRANSFER MODE REGISTER This register is used to control the operation of data transfers. The Host Driver shall set this register before issuing a command which transfers data (see Data Present Select in the Command register), or before issuing a Resume command. The Host Driver shall save the value of this register when the data transfer is suspended (as a result of a Suspend command) and restore it before issuing a Resume command.
PAGE 522
HSMMC CONTROLLER Name Bit ENBLKCNT [1] S3C2450X RISC MICROPROCESSOR Description Initial Value 0 Block Count Enable This bit is used to enable the Block Count register, which is only relevant for multiple block transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing an infinite transfer. (Refer to the Table below ″Determination of Transfer Type″ ) 1 = Enable 0 = Disable ENDMA [0] 0 DMA Enable This bit enables DMA functionality.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.7 COMMAND REGISTER This register contains the SD Command Argument. Register Address R/W Description Reset Value CMDREG0 0X4AC0000E R/W Command Register (Channel 0) 0x0 CMDREG1 0X4A80000E R/W Command Register (Channel 1) 0x0 The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit (CMD) bit in the Present State register before writing to this register.
PAGE 524
HSMMC CONTROLLER Name Bit DATAPRNT [5] S3C2450X RISC MICROPROCESSOR Description Initial Value Data Present Select This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0 for the following: (1) Commands using only CMD line (ex. CMD52). (2) Commands with no data transfer but using busy signal on DAT[0] line (R1b or R5b ex.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER NOTES: 1. In the SDIO specification, response type notation of R5b is not defined. R5 includes R5b in the SDIO specification. But R5b is defined in this specification to specify the Host Controller shall check busy after receiving response. For example, usually CMD52 is used as R5 but I/O abort command shall be used as R5b. 2. For CMD52 to read BS after writing "Bus Suspend," Command Type should be "Suspend" as well. 5.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR The Response Field indicates bit positions of “Responses” defined in the PHYSICAL LAYER SPECIFICATION Version 1.01. The Table (upper) shows that most responses with a length of 48 (R[47:0]) have 32 bits of the response data (R[39:8]) stored in the Response register at REP[31:0]. Responses of type R1b (Auto CMD12 responses) have response data bits R[39:8] stored in the Response register at REP[127:96].
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.9 BUFFER DATA PORT REGISTER 32-bit data port register to access internal buffer. Register Address R/W BDATA0 0X4AC00020 R/W Buffer Data Register (Channel 0) − BDATA1 0X4A800020 R/W Buffer Data Register (Channel 1) − Name BUFDAT Bit [31:0] Description Reset Value Description Initial Value The Host Controller buffer can be accessed through this 32-bit Data Port register.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.10 PRESENT STATE REGISTER This register contains the SD Command Argument.
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S3C2450X RISC MICROPROCESSOR Name Bit HSMMC CONTROLLER Description Initial Value 0 = Reset or Debouncing INSCARD [16] Card Inserted (RO) 0 This bit indicates whether a card has been inserted. The Host Controller shall debounce this signal so that the Host Driver will not need to wait for it to stabilize.
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HSMMC CONTROLLER Name BUFWTRDY S3C2450X RISC MICROPROCESSOR Bit [10] Description Buffer Write Enable (ROC) Initial Value 0 This status is used for non-DMA write transfers. The Host Controller can implement multiple buffers to transfer data efficiently. This read only flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to the buffer.
PAGE 531
S3C2450X RISC MICROPROCESSOR Name Bit [7:3] DATLINEACT [2] HSMMC CONTROLLER Description Initial Value Reserved 0 DAT Line Active (ROC) 0 This bit indicates whether one of the DAT line on SD Bus is in use. (a) In the case of read transactions This status indicates if a read transfer is executing on the SD Bus. Changes in this value from 1 to 0 between data blocks generate a Block Gap Event interrupt in the Normal Interrupt Status register.
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HSMMC CONTROLLER Name Bit S3C2450X RISC MICROPROCESSOR Description Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal Interrupt Status register. Initial Value Note: The SD Host Driver can save registers in the range of 00000Dh for a suspend transaction after this bit has changed from 1 to 0.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER Figure 21-14. Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer Figure 21-15. Timing of Command Inhibit (DAT) for the case of response with busy Figure 21-16.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.11 HOST CONTROL REGISTER This register contains the SD Command Argument.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.12 POWER CONTROL REGISTER This register contains the SD Command Argument. Register Address R/W PWRCON0 0X4AC00029 R/W Present State Register (Channel 0) 0x0 PWRCON1 0X4A800029 R/W Present State Register (Channel 1) 0x0 Name SELPWRLVL Description Bit Description [7:4] Reserved [3:1] SD Bus Voltage Select Reset Value Initial Value 0 By setting these bits, the Host Driver selects the voltage level for the SD card.
PAGE 536
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.13 BLOCK GAP CONTROL REGISTER This register contains the SD Command Argument.
PAGE 537
S3C2450X RISC MICROPROCESSOR Name Bit HSMMC CONTROLLER Description Initial Value This bit is used to stop executing a transaction at the next block gap for both DMA and non-DMA transfers. Until the Transfer Complete is set to 1, indicating a transfer completion the Host Driver shall leave this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request shall not cause the transaction to restart. Read Wait is used to stop the read transaction at the block gap.
PAGE 538
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.14 WAKEUP CONTROL REGISTER This register is mandatory for the Host Controller, but wakeup functionality depends on the Host Controller system hardware and software. The Host Driver shall maintain voltage on the SD Bus, by setting SD Bus Power to 1 in the Power Control register, when wakeup event via Card Interrupt is desired.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.15 CLOCK CONTROL REGISTER At the initialization of the Host Controller, the Host Driver shall set the SDCLK Frequency Select according to the Capabilities register.
PAGE 540
HSMMC CONTROLLER Name STBLEXTCLK S3C2450X RISC MICROPROCESSOR Bit [3] Description External Clock Stable Initial Value 0 This bit is set to 1 when SD Clock output is stable after writing to SD Clock Enable in this register to 1. The SD Host Driver shall wait to issue command to start until this bit is set to 1. (ROC) 1 = Ready 0 = Not Ready ENSDCLK [2] SD Clock Enable 0 The Host Controller shall stop SDCLK when writing this bit to 0. SDCLK Frequency Select can be changed when this bit is 0.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.16 TIMEOUT CONTROL REGISTER At the initialization of the Host Controller, the Host Driver shall set the Data Timeout Counter Value according to the Capabilities register.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.17 SOFTWARE RESET REGISTER A reset pulse is generated when writing 1 to each bit of this register. After completing the reset, the Host Controller shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall confirm that these bits are 0.
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S3C2450X RISC MICROPROCESSOR Name Bit RSTDAT [0] HSMMC CONTROLLER Description Software Reset For All Initial Value 0 This reset affects the entire Host Controller except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the Host Driver shall set this bit to 1 to reset the Host Controller. The Host Controller shall reset this bit to 0 when capabilities registers are valid and the Host Driver can read them.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.18 NORMAL INTERRUPT STATUS REGISTER The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not affect these reads. An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1. For all bits except Card Interrupt and Error Interrupt, writing 1 to a bit clear it; writing to 0 keeps the bit unchanged.
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S3C2450X RISC MICROPROCESSOR Name Bit HSMMC CONTROLLER Description detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the SD card and the interrupt to the Host System. It is necessary to define how to handle this delay.
PAGE 546
HSMMC CONTROLLER Name STADMAINT S3C2450X RISC MICROPROCESSOR Bit [3] Description DMA Interrupt Initial Value 0 This status is set if the Host Controller detects the Host DMA Buffer boundary during transfer. Refer to the Host DMA Buffer Boundary in the Block Size register. Other DMA interrupt factors may be added in the future. This interrupt shall not be generated after the Transfer Complete.
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S3C2450X RISC MICROPROCESSOR Name Bit HSMMC CONTROLLER Description than Data Timeout Error. If both bits are set to 1, the data transfer can be considered complete.
PAGE 548
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.19 ERROR INTERRUPT STATUS REGISTER Signals defined in this register can be enabled by the Error Interrupt Status Enable register, but not by the Error Interrupt Signal Enable register. The interrupt is generated when the Error Interrupt Signal Enable is enabled and at least one of the statuses is set to 1. Writing to 1 clears the bit and writing to 0 keeps the bit unchanged. More than one status can be cleared at the one register write.
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S3C2450X RISC MICROPROCESSOR Name Bit HSMMC CONTROLLER Description Initial Value Occurs when detecting one of following timeout conditions. (1) Busy timeout for R1b,R5b type (2) Busy timeout after Write CRC status (3) Write CRC Status timeout (4) Read Data timeout. 1 = Timeout 0 = No Error STACMDIDXERR [3] Command Index Error 0 Occurs if a Command Index error occurs in the command response.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR The relation between Command CRC Error and Command Timeout Error is shown in Table below. Table 21-4.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.20 NORMAL INTERRUPT STATUS ENABLE REGISTER Setting to 1 enables Interrupt Status.
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HSMMC CONTROLLER Name S3C2450X RISC MICROPROCESSOR Bit ENSTACARDNS Initial Value Card Insertion Status Enable [6] ENSTABUFRDRDY 1 = Enabled 0 = Masked 0 Buffer Read Ready Status Enable [5] ENSTABUFWTRDY 1 = Enabled 0 = Masked 0 Buffer Write Ready Status Enable [4] ENSTADMA 1 = Enabled 0 = Masked 0 DMA Interrupt Status Enable [3] ENSTABLKGAP 1 = Enabled 0 = Masked 0 Block Gap Event Status Enable [2] ENSTASTANSCMPLT 1 = Enabled 0 = Masked 0 Transfer Complete Status Enable [1] ENSTAC
PAGE 553
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.21 ERROR INTERRUPT STATUS ENABLE REGISTER Setting to 1 enables Error Interrupt Status.
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HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.22 NORMAL INTERRUPT SIGNAL ENABLE REGISTER This register is used to select which interrupt status is indicated to the Host System as the interrupt. These status bits all share the same1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.
PAGE 555
S3C2450X RISC MICROPROCESSOR Name ENSIGBUFRDRDY Bit [5] HSMMC CONTROLLER Description Buffer Read Ready Signal Enable Initial Value 0 1 = Enabled 0 = Masked ENSIGBUFWTRDY [4] Buffer Write Ready Signal Enable 0 1 = Enabled 0 = Masked ENSIGDMA [3] DMA Interrupt Signal Enable 0 1 = Enabled 0 = Masked ENSIGBLKGAP [2] Block Gap Event Signal Enable 0 1 = Enabled 0 = Masked ENSIGSTANSCMPLT [1] Transfer Complete Signal Enable 0 1 = Enabled 0 = Masked ENSIGCMDCMPLT [0] Command Complete Signal
PAGE 556
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.23 ERROR INTERRUPT SIGNAL ENABLE REGISTER This register is used to select which interrupt status is notified to the Host System as the interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.
PAGE 557
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.24 AUTOCMD12 ERROR STATUS REGISTER When Auto CMD12 Error Status is set, the Host Driver shall check this register to identify what kind of error Auto CMD12 indicated. This register is valid only when the Auto CMD12 Error is set.
PAGE 558
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR The relation between Auto CMD12 CRC Error and Auto CMD12 Timeout Error is shown below. Table 21-5.
PAGE 559
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.25 CAPABILITIES REGISTER This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset for All in the Software Reset register for loading from flash memory and completion timing control.
PAGE 560
HSMMC CONTROLLER Name CAPAMAXBLKLEN S3C2450X RISC MICROPROCESSOR Bit Description [17:16] Max Block Length (HWInit) Initial Value 0 This value indicates the maximum block size that the Host Driver can read and write to the buffer in the Host Controller. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below.
PAGE 561
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.26 MAXIMUM CURRENT CAPABILITIES REGISTER These registers indicate maximum current capability for each voltage. The value is meaningful if Voltage Support is set in the Capabilities register. If this information is supplied by the Host System via another method, all Maximum Current Capabilities register shall be 0.
PAGE 562
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.27 CONTROL REGISTER 2 Register Address R/W Description CONTROL2_0 0X4AC00080 R/W Control register 2 (Channel 0) 0x0 CONTROL2_1 0X4A800080 R/W Control register 2 (Channel 1) 0x0 Name Bit [31] Description Write Status Clear Async Mode Enable Reset Value Initial Value 0 This bit can make async-clear enable about Normal and Error interrupt status bit. During the initialization procedure command operation, this bit should be enabled.
PAGE 563
S3C2450X RISC MICROPROCESSOR Name Bit HSMMC CONTROLLER Description Initial Value Card Detect Pin Level does not simply reflect SDCD# pin, but chooses from SDCD, DAT[3], or CDTestlvl depending on CDSigSel and this field (SDCDSel) values 0 = nSDCD is used for SD Card Detect Signal 1 = DAT[3] is used for SD Card Detect Signal CDSYNCSEL [12] SD Card Detect Sync Support 0 This field is used to enable output CMD and DAT referencing SD Bus Power bit in the “PWRCON register”, when being set.
PAGE 564
HSMMC CONTROLLER Name PWRSYNC S3C2450X RISC MICROPROCESSOR Bit [3] Description SD OP Power Sync Support with SD Card Initial Value 0 This field is used to enable input CMD and DAT referencing SD Bus Power bit in the “PWRCON register”, when being set.
PAGE 565
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.
PAGE 566
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.29 DEBUG REGISTER Register Address R/W DEBUG_0 0X4AC00088 R/W DEBUG register (Channel 0) Not fixed DEBUG_1 0X4A800088 R/W DEBUG register (Channel 1) Not fixed Name DBGREG Bit [31:0] Description Description Reset Value Initial Value Not fixed Debug Register Read Only Register for Debug Purpose (RO) 5.
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S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.31 FORCE EVENT REGISTER FOR AUTO CMD12 ERROR STATUS Register Address R/W Description Reset Value FEAER0 0X4AC00050 WO Force Event Auto CMD12 Error Interrupt Register Error Interrupt (Channel 0) 0x0000 FEAER1 0X4A800050 WO Force Event Auto CMD12 Error Interrupt Register Error Interrupt (Channel 1) 0x0000 The Force Event Register is not a physically implemented register.
PAGE 568
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.32 FORCE EVENT REGISTER FOR ERROR INTERRUPT STATUS Register Address R/W Description Reset Value FEERR0 0X4AC00052 WO Force Event Error Interrupt Register Error Interrupt (Channel 0) 0x0000 FEERR1 0X4A800052 WO Force Event Error Interrupt Register Error Interrupt (Channel 1) 0x0000 The Force Event Register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written.
PAGE 569
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.33 ADMA ERROR STATUS REGISTER When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor.
PAGE 570
HSMMC CONTROLLER Name S3C2450X RISC MICROPROCESSOR Bit [1:0] Description ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "10" because ADMA never stops in this state.
PAGE 571
S3C2450X RISC MICROPROCESSOR HSMMC CONTROLLER 5.34 ADMA SYSTEM ADDRESS REGISTER This register contains the physical Descriptor address used for ADMA data transfer.
PAGE 572
HSMMC CONTROLLER S3C2450X RISC MICROPROCESSOR 5.35 HOST CONTROLLER VERSION REGISTER Register Address R/W HCVER0 0X4AC000FE HWInit Host Controller Version Register (Channel 0) 0x0401 HCVER1 0X4A8000FE HWInit Host Controller Version Register (Channel 1) 0x0401 Name VENVER Description Bit [15:8] Description Vendor Version Number Reset Value Initial Value 0x04 This status is reserved for the vendor version number. The Host Driver should not use this status. 0x04 = SDMMC4.
PAGE 573
S3C2450X RISC MICROPROCESSOR 22 LCD CONTROLLER LCD CONTROLLER 1 OVERVIEW The LCD controller consists of logic for transferring image data from a video buffer located in system memory to an external LCD driver interface. LCD driver interface has two kind of interface. One is conventional RGBinterface and the other is i80-System interface.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 1.1 FEATURES 1.1.
PAGE 575
S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 2 FUNCTIONAL DESCRIPTION 2.1 BRIEF OF THE SUB-BLOCK The LCD controller consists of a VSFR, VDMA, VPRCS, VTIME, and video clock generator. The VSFR has 71 programmable register sets and two-256x25 palette memory, which are used to configure the LCD controller. The VDMA is a dedicated LCD DMA, which it can transfer the video data in frame memory to VPRCS. By using this special DMA, the video data can be displayed on the screen without CPU intervention.
PAGE 576
LCD CONTROLLER S3C2450X RISC MICROPROCESSOR AMBA CH0 CH1 RGB RGB Win0(RGB) Win1(RGB) Blending Color key OUTPUT(RGB) Figure 22-2. Block diagram of the Data Flow 2.3 INTERFACE LCD controller supports 2 types of display device. One type is the conventional RGB-interface that uses RGB data, Vertical/horizontal sync, data valid signal and data sync clock. The Second type is i80-System interface that uses address, data, chip select, read/write control and register/status indicating signal.
PAGE 577
S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 2.4 OVERVIEW OF THE COLOR DATA 2.4.1 RGB Data format The LCD controller requests the specified memory format of frame buffer. The next table shows some examples of each display mode. 2.4.2 28BPP display (A4+888) (BSWP = 0, HWSWP = 0, BLD_PIX = 1, ALPHA_SEL = 1) D[31:28] D[27:24] D[23:0] 000H Dummy Bit Alpha value P1 004H Dummy Bit Alpha value P2 008H Dummy Bit Alpha value P3 ... P1 P2 P3 P4 P5 ......
PAGE 578
LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 2.4.3 25BPP display (A888) (BSWP = 0, HWSWP = 0) D[31:25] D[24] D[23:0] 000H Dummy Bit AEN P1 004H Dummy Bit AEN P2 008H Dummy Bit AEN P3 ... P1 P2 P3 P4 P5 ...... LCD Panel NOTES: 1. AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN = 0 : ALPHA0_R/G/B values are applied. AEN = 1 : ALPHA1_R/G/B values are applied. Each pixel of LCD panel displays blended color with lower layer window.
PAGE 579
S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 2.4.4 24BPP display (A887) (BSWP = 0, HWSWP = 0) D[31:24] D[23] D[22:0] 000H Dummy Bit AEN P1 004H Dummy Bit AEN P2 008H Dummy Bit AEN P3 ... P1 P2 P3 P4 P5 ...... LCD Panel NOTES: 1. AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN = 0 : ALPHA0_R/G/B values are applied. AEN = 1 : ALPHA1_R/G/B values are applied. Each pixel of LCD panel displays blended color with lower layer window.
PAGE 580
LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 2.4.5 24BPP display (888) (BSWP = 0, HWSWP = 0) D[31:24] D[23:0] 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 ... P1 P2 P3 P4 P5 ......
PAGE 581
S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 2.4.6 19BPP display (A666) (BSWP = 0, HWSWP = 0) D[31:19] D[18] D[17:0] 000H Dummy Bit AEN P1 004H Dummy Bit AEN P2 008H Dummy Bit AEN P3 ... P1 P2 P3 P4 P5 ...... LCD Panel NOTES: 1. AEN : Select Alpha value in Window 1 Alpha Value Register for alpha blending AEN = 0 : ALPHA0_R/G/B values are applied. AEN = 1 : ALPHA1_R/G/B values are applied. Each pixel of LCD panel displays blended color with lower layer window.
PAGE 582
LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 2.4.7 18BPP display (666) (BSWP = 0, HWSWP = 0) D[31:18] D[17:0] 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 ... P1 P2 P3 P4 P5 ...... LCD Panel P1 P2 P3 P4 P5 ......
PAGE 583
S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 2.4.8 16BPP display (A555) (BSWP = 0, HWSWP = 0) D[31] D[30:16] D[15] D[14:0] 000H AEN1 P1 AEN2 P2 004H AEN3 P3 AEN4 P4 008H AEN5 P5 AEN6 P6 [31] D[30:16] D[15] D[14:0] 000H AEN2 P2 AEN1 P1 004H AEN4 P4 AEN3 P3 008H AEN6 P6 AEN5 P5 ... (BSWP = 0, HWSWP = 1) ... P1 P2 P3 P4 P5 ...... LCD Panel NOTES: 1.
PAGE 584
LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 2.4.9 16BPP display (1+555) (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H P1 P2 004H P3 P4 008H P5 P6 ... (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H P2 P1 004H P4 P3 008H P6 P5 ... NOTE: {D[14:10], D[15] } = Red data, {D[9:5], D[15] } = Green data, {D[4:0], D[15]}= Blue data Figure 22-3.
PAGE 585
S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 2.4.10 16BPP display (565) (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H P1 P2 004H P3 P4 008H P5 P6 ... (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H P2 P1 004H P4 P3 008H P6 P5 ... NOTE: D[15:11] = Red data, D[10:5] = Green data, D[4:0] = Blue data Figure 22-4.
PAGE 586
LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 2.4.11 8BPP display (A232) (BSWP = 0, HWSWP = 0) D[31] D[30:24] D[23] D[22:16] D[15] D[14:8] D[7] D[6:0] 000H AEN1 P1 AEN2 P2 AEN3 P3 AEN4 P4 004H AEN5 P5 AEN6 P6 AEN7 P7 AEN8 P8 008H AEN9 P9 AEN10 P10 AEN11 P11 AEN12 P12 D[31] D[30:24] D[23] D[22:16] D[15] D[14:8] D[7] D[6:0] 000H AEN4 P4 AEN3 P3 AEN2 P2 AEN1 P1 004H AEN8 P8 AEN7 P7 AEN6 P6 AEN5 P5 008H AEN12 P12 AEN11 P11 AEN10 P10 AEN9 P9 .
PAGE 587
S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 2.4.12 8BPP display (Palette) (BSWP = 0, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H P1 P2 P3 P4 004H P5 P6 P7 P8 008H P9 P10 P11 P12 D[31:24] D[23:16] D[15:8] D[7:0] 000H P4 P3 P2 P1 004H P8 P7 P6 P5 008H P12 P11 P10 P9 ... (BSWP = 1, HWSWP = 0) ... P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 ...... LCD Panel NOTE: The values of frame buffer are index of palette memory.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 2.4.13 4BPP display (Palette) (BSWP = 0, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H P1 P2 P3 P4 P5 P6 P7 P8 004H P9 P10 P11 P12 P13 P14 P15 P16 008H P17 P18 P19 P20 P21 P22 P23 P24 D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H P7 P8 P5 P6 P3 P4 P1 P2 004H P15 P16 P13 P14 P11 P12 P9 P10 008H P23 P24 P21 P22 P19 P20 P17 P18 ...
PAGE 589
S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 2.4.14 2BPP display (Palette) (BSWP = 0, HWSWP = 0) [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] 002H P1 P2 P3 P4 P5 P6 P7 P8 006H P17 P18 P19 P20 P21 P22 P23 P24 00AH P33 P34 P35 P36 P37 P38 P39 P40 [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 000H P9 P10 P11 P12 P13 P14 P15 P16 004H P25 P26 P27 P28 P29 P30 P31 P32 008H P41 P42 P43 P44 P45 P46 P47 P48 … ... 2.4.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 2.5 VD SIGNAL CONNECTION 2.5.1 VD Pin Descriptions at 24BPP RGB parallel VD 23 22 21 20 19 18 17 16 RED 7 6 5 4 3 2 1 0 GREEN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BLUE 2.5.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 2.5.6 VD Pin Descriptions at 18BPP i80-System Interface VD 23 22 21 20 19 18 RED 17 16 15 14 13 12 5 4 3 2 1 0 NC GREEN 11 10 9 8 7 6 5 4 3 2 1 0 BLUE 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 2.5.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 2.6 PALETTE USAGE 2.6.1 Palette Configuration and Format Control The LCD controller can support the 256 colors palette for various selection of color mapping. The user can select 256 colors from the 24-bit colors through these four formats. 256 colors palette consist of the 256(depth) × 25-bit DPSRAM. Palette supports 8:8:8, 6:6:6, 5:6:5(R:G:B), and etc format.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER Table 22-2. 19BPP (A:6:6:6) Palette Data Format 24 23 22 21 20 19 00H - - - - 01H - - - ....... - - FFH - Number of - INDEX\Bit Pos.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 3 WINDOW BLENDING 3.1 OVERVIEW The main function of the VPRCS module is window blending. LCD controller has 2-window layers and the detail is described below. As an example of application, System can use win0 as an OS window, full TV screen window or etc. This feature enhances the system performance by reducing the data rate of total system. 3.1.1 Total 2 windows Window 0 (base) : RGB with palette Window 1 (overlay) : RGB with palette 3.1.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 3.2 BLENDING DIAGRAM/DETAILS LCD controller could blend 2-Layer for the only one pixel at the same time. The Blending factor, alpha value is controlled by ALPHA0_R/G/B and ALPHA1_R/G/B fields in Window 1 Alpha Value register or DATA[27:24] in frame buffer, which are implemented for each window layer and color(R,G,B). As a special feature, between two windows have two kinds of alpha blending value. One is ALPHA0_R/G/B(AEN=0) and the other is ALPHA1_R/G/B(AEN=1).
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR COMPKEY Mask bit of COLVAL to compare with Window color DIRCON Window0 (Background) COLVAL Frame Buffer R’G’B’ Compare Selected Window Match with COLVAL : Unselected window Unmatched with CONVAL : Selected window Window1 (Foreground) Figure 22-6.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER OSD Image 180x100 Back-Ground 320x240 Blended (Alpha = 0xf) and No Color key Blended (Alpha = 0x9) and No Color key Blended (Alpha = 0x0) No Blend and Color Key Enable Blended (Alpha = 0x9) and Color Key Enable Figure 22-8.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 4 VTIME CONTROLLER OPERATION 4.1 RGB INTERFACE The VTIME generates the control signals such as, RGB_VSYNC, RGB_HSYNC, RGB_VDEN and RGB_VCLK signal for RGB interface. These control signals are highly related with the configuration on the VIDTCON0/1/2 registers in the VSFR register.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 5 VIRTUAL DISPLAY The LCD controller supports the hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL registers need to be changed (refer to Figure 22-9), but PAGEWIDTH and OFFSIZE value do not change. The size of video buffer in which the image is stored should be larger than the LCD panel screen size. OFFSIZE PAGEWIDTH OFFSIZE This is the data of line 1 of virtual screen.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 6 RGB INTERFACE I/O 6.1.1 Signals Name Type Description RGB_HSYNC Output Horizontal Sync. Signal RGB_VSYNC Output Vertical Sync. Signal RGB_VCLK Output LCD Video Clock RGB_VDEN Output Data Enable RGB_VD[23:0] Output RGB data output 6.1.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 7 LCD CPU INTERFACE I/O (i80-SYSTEM I/F) 7.1.1 Signals Name Type Description SYS_VD[17:0] InOut Video Data SYS_CS0 Output Chip select for Main LCD SYS_CS1 Output Chip select for Sub LCD SYS_WR Output Write enable SYS_OE Output Output enable SYS_RS Output Register/State select 7.1.2 CPU (i80-System) I/F Timing Figure 22-11.
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LCD CONTROLLER 7.1.3 S3C2450X RISC MICROPROCESSOR LCD signal Muxing Table 22-6.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8 PROGRAMMER’S MODEL 8.1 OVERVIEW The following registers are used to configure LCD controller 1. VIDCON0: Configure Video output format and display enable/disable. 2. VIDCON1: RGB I/F control signal. 3. SYSIFCONx: i80-System I/F control signal. 4. VIDTCONx: Configure Video output Timing and determine the size of display. 5. WINCONx: Each window format setting 6. VIDOSDxA, VIDOSDxB: Window position setting 7. VIDOSDxC: Alpha value setting 8.
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LCD CONTROLLER Register S3C2450X RISC MICROPROCESSOR Address R/W Description Reset Value VIDW00ADD2B0 0x4C800094 R/W Window 0’s buffer size register, buffer 0 0x0000_0000 VIDW00ADD2B1 0x4C800098 R/W Window 0’s buffer size register, buffer 1 0x0000_0000 VIDW01ADD2 0x4C80009C R/W Window 1’s buffer size register 0x0000_0000 VIDINTCON 0x4C8000AC R/W Indicate the Video interrupt control register 0x03F0_0000 W1KEYCON0 0x4C8000B0 R/W Color key control register 0x0000_0000 W1KEYCON1
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8.1.2 Video Main Control 0 Register Register VIDCON0 VIDCON0 Address R/W 0x4C800000 R/W Bit Description Video control 1 register Description Reset Value 0x0000_0000 Initial State Reserved [31:24] Reserved VIDOUT [23:22] It determines the output format of LCD Controller 00 = RGB I/F 01 = Reserved 10 = i80-System I/F for Main LDI 11 = i80-System I/F for Sub LDI L1_DATA16 [21:19] Select the mode of output data format of i80-System I/F (Sub LDI.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.3 Video Main Control 0 Register (Continued) VIDCON0 Bit Description Initial State CLKVALUP [12] Select CLKVAL_F Update timing control 0 = Always 1 = Start of a frame (Only once per frame) 0 CLKVAL_F [11:6] Determine the rates of VCLK. VCLK = (HCLK or LCD video Clock) / [CLKVAL+1] ( CLKVAL ≥ 1 ) 0 VCLKEN [5] VCLK Enable Control 0 = Disable 1 = Enable 0 CLKDIR [4] Select the clock source as direct or divide using CLKVAL_F register.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8.1.4 Video Main Control 1 Register Register VIDCON1 VIDCON1 Address R/W 0x4C800004 R/W Description Video control 2 register Bit LINECNT (read only) [26:16] Reserved [15] VSTATUS [14:13] Description Reset Value 0x0000_0000 Initial state Provide the status of the line counter (read only) Up count from 0 to LINEVAL 0 Reserved 0 Vertical Status (read only).
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.6 Video Time Control 1 Register Register VIDTCON1 VIDTCON1 HBPD Address R/W 0x4C80000C R/W Bit [23:16] Description Video time control 2 register Description Horizontal back porch is the number of VCLK periods between the edge of HSYNC and the start of active data.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8.1.8 Window 0 Control Register Register WINCON0 Address R/W 0x4C800014 R/W WINCON0 Bit BUFSTATUS [24] BUFSEL [23] BUFAUTOEN [22] Description Window 0 control register Description Status of Current display Buffer (Read only) 0 = buffer0 display 1 = buffer1 display Reset Value 0x0000_0000 Initial State 0 Note: RGB I/F does not support auto-change mode. Only i80-Sytem I/F supports auto-change mode.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.
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S3C2450X RISC MICROPROCESSOR WINCON1 Bit LCD CONTROLLER Description Per pixel blending case( BLD_PIX ==1) 0 = selected by AEN bit in frame buffer for each pixel or Key area 0 KEYBLEND (W1KEYCON0[26]) 1 AEN = 0 ALPHA0_R/G/B AEN = 1 ALPHA1_R/G/B Non-Key area ALPHA0_R/G/B Key area ALPHA1_R/G/B Initial State 1 = using DATA[27:24] in frame buffer, only for 28bpp mode ENWIN_F [0] Window1 on/ off control 0 = Off window1 1 = On window1 0 8.1.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.12 Window 1 Position Control A Register Register VIDOSD1A VIDOSD1A Address R/W 0x4C800034 R/W Description Video Window 1’s position control 2 register Bit Description Reset Value 0x0000_0000 initial state OSD_LeftTopX_F [21:11] Horizontal screen coordinate for left top pixel of OSD image 0 OSD_LeftTopY_F [10:0] Vertical screen coordinate for left top pixel of OSD image 0 8.1.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8.1.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8.1.18 VIDEO Interrupt Control Register Register VIDINTCON Address R/W 0x4C8000AC R/W Description Indicate the Video interrupt control register 0x3F00000 VIDINTCON Bit FIFOINTERVAL [25:20] These bits control the interval of the FIFO interrupt. 0x3F SYSMAINCON [19] Sending complete interrupt enable bit to Main LCD 0 = Interrupt Disable. 1 = Interrupt Enable.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8.1.20 WIN 1 Color key 1 Register Register W1KEYCON1 W1KEYCON1 COLVAL Address R/W 0x4C8000B4 R/W Description Color key value ( transparent value) register Bit [23:0] Description Color key value for the transparent pixel effect Reset Value 0x0000_0000 Initial state 0 NOTE: COLVAL and COMPKEY use 24-bit color data at all bpp mode. Unused higher bits should be ‘1b’. @ BPP24 mode: 24-bit color value is valid. A.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.21 WIN0 Color MAP Register WIN0MAP WIN0MAP MAPCOLEN_F MAPCOLOR Address R/W 0x4C8000D0 R/W Bit [24] [23:0] Description Window color control Description Reset Value 0x0000_0000 Initial state Window’s color mapping control bit. If this bit is enabled then Video DMA will stop, and MAPCOLOR will be appear on back-ground image instead of original image. 0 = disable 1 = enable 0 Color Value 0 8.1.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8.1.23 Window Palette control Register Register WPALCON Address R/W Description Reset Value 0x4C8000E4 R/W Window Palette control register 0x0000_0000 WPALCON Bit Description Initial state PALUPDATEEN [9] Palette memory access-right control bit. Users should set this bit before access (write or read) palette memory, in this case LCD controller cannot access palette. After update, users should clear this bit for operation of palletized LCD.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8.1.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.
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S3C2450X RISC MICROPROCESSOR LCD CONTROLLER 8.1.27 i80-System Interface Command Control 1 Register SIFCCON1 SIFCCON1 Address R/W Description Reset Value 0x4C800140 R/W i80-System Interface Command Data Write register 0x0000_0000 Bit Description Initial State Reserved [23:18] Reserved 0 SYS_WDATA [17:0] LCD i80-System Interface Write Data 0 8.1.
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LCD CONTROLLER S3C2450X RISC MICROPROCESSOR 8.1.29 i80-System I/F TRIGGER CONTROL 2 Register Register Address R/W CPUTRIGCON2 0x4C800160 R/W CPUTRIGCON2 Bit SWTRIG [0] Description Software-Based Trigger control register Description Reset Value 0x0000_0000 Initial State Software-Based Transmission Trigger When this bit is set, trigger happens. This bit is automatically cleared. Trigger function is valid only when the LCD is enabled state. (ENVID=’11b’) 0 8.1.
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S3C2450X RISC MICROPROCESSOR 23 CAMERA INTERFACE CAMERA INTERFACE 1 OVERVIEW This specification defines the interface of camera. The CAMIF (Camera Interface) within the S3C2450X consists of eight parts. They are the pattern mux, capturing unit, MSDMA (Memory Scaling DMA), preview scaler, codec scaler, preview DMA, codec DMA, and SFR. The camera interface supports ITU R BT-601/656 YCbCr 8-bit standard and Memory. Maximum input size is 4096x4096 pixels (2048x2048 pixels for scaling).Two scalers exist.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 1.1 FEATURES • ITU-R BT 601/656 8-bit mode support • DZI (Digital Zoom In) capability • Programmable polarity of video sync signals • Max. 4096 x 4096 pixels input support (non-scaling) • Max.
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 2.2 TIMING DIAGRAM 1 frame VSYNC Vertical lines HREF HREF (1H) Horizontal width PCLK 8-bit mode DATA[7:0] Y Cb Y Cr Y Cb Y Cb Y Cr Figure 23-2. ITU-R BT 601 Input Timing Diagram FieldMode = 1 (Field port connects with FIELD) Field 1 Field 2 FIELD VSYN C Figure 23-3.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR There are two timing reference signals in ITU-R BT 656 format, one at the beginning of each video data block (start of active video, SAV) and one at the end of each video data block(end of active video, EAV) as shown in Figure 23-3 and below table. Table 23-2.
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 3 EXTERNAL/INTERNAL CONNECTION GUIDE All CAMIF input signals should not occur inter-skewing to pixel clock line. CAMCLK CAMRST CAMIF No Skew VSYNC Camera A HREF PCLK PDATA[7:0] Figure 23-6. IO Connection Guide 4 CAMERA INTERFACE OPERATION 4.1 TWO DMA PORTS CAMIF has two DMA port. P-port(Preview port) and C-port(Codec port) are separated from each other on AHB bus. At the view of system bus, two ports are independent.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR Frame Memory (SDRAM) P-port External Camera Processor CAMIF ITU format C-port P-port CAMIF ITU format C-port Figure 23-7.
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 4.2 CLOCK DOMAIN CAMIF has two clock domains. The one is the system bus clock, which is HCLK. The other is the pixel clock, which is PCLK. The system clock must be faster than pixel clock. As shown in figure 23-8, CAMCLK must be divided from the fixed frequency like USB PLL clock. If external clock oscillator were used, CAMCLK should be floated. Internal scaler clock is system clock. It is not necessary for two clock domains to be synchronized each other.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 4-pingpong Frame memory (SDRAM) P-port RGB 1 P-port RGB 2 P-port RGB 3 P-port RGB 4:4:4 ITU-601/656 YCbCr 4:2:2 8-bits Camera Interface P-port RGB 4 AHB bus & Memorycontroller C-port Y 1 / RGB 1 C-port Cb 1 C-port YCbCr 4:2:0,2 RGB 4;4:4 C-port Cr 1 C-port Y 2 / RGB 2 C-port Cb 2 C-port Cr 2 C-port Y 3 / RGB 3 C-port Cb 3 C-port Cr 3 C-port Y 4 / RGB 4 C-port Cb 4 C-port Cr 4 Figure 23-9.
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 4.4 MEMORY STORING METHOD The storing method to the frame memory is the little-endian method in codec path. The first entering pixels stored into LSB sides, and the last entering pixels stored into MSB sides. The carried data by AHB bus is 32-bit word. So, CAMIF make the each Y-Cb-Cr words by little endian style. For RGB format, two different formats exist. One pixel (Color 1 pixel) is one word for RGB 24-bit format.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 4.5 TIMING DIAGRAM FOR REGISTER SETTING The first register setting for frame capture command can be occurred in anywhere of frame period. But, it is recommend to do first setting at the VSYNC “L” state. VSYNC information can be read from status SFR. Refer to the below figure. All command include ImgCptEn, is valid at VSYNC falling edge. Be sure that except first SFR setting, all command should be programmed in ISR(Interrupt Service Routine).
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE VSYNC HREF INTERRUPT Multi frame capturing Reserved Image Capture SFR setting (ImgCptEn) < Frame Capture Start for external camera input > VSYNC HREF INTERRUPT In Capturing Image Capture Reserved New Command New SFR command < New command valid timing diagram > Read Memory SFR setting (ENVID_MS) Image Capture SFR setting (ImgCptEn_PrSc) SEL_DMA_CAM SFR setting (SEL_DMA_CAM) < Frame Capture Start for MSDMA memory input > PIPDMA end PreviewDMA end Read Mem
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 4.5.1 Timing diagram for Last IRQ (Camera capture mode) IRQ except LastIRQ is generated before image capturing. Last IRQ which means capture-end can be set by following timing diagram. LastIRQEn is auto-cleared and ,as mentioned, SFR setting in ISR is for next frame command. So, for adequate last IRQ, you should follow next sequence between LastIRQEn and ImgCptEn/ImgCptEn_CoSc/ImgCptEnPrSC.
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S3C2450X RISC MICROPROCESSOR SFR region CAMERA INTERFACE SFR region SFR region SFR region SFR region SFR region SFR region ENVID_MS FrameCnt ++ ImgCptEn_PrSC Preview DMA frame done (internal signal) IRQ FrameCnt 3 0 1 1 Capture O (Frame_3) Capture O (Frame_0) Capture X 2 Capture O (Frame_1) 3 0 Capture O (Frame_2) Capture O (Frame_3) Figure 23-12. Timing Diagram for Last IRQ 4.6 MSDMA FEATURE MSDMA supports memory data scaling.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 5 SOFTWARE INTERFACE CAMIF SFR (Special Function Register) 6 CAMERA INTERFACE SPECIAL REGISTERS • When preview input use MSDMA path, the first column mark (v) sfr will be related to the preview operation. • The last column means that each value can change by each VSYNC start during capture enable. (O : change , X : not change) 6.
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.2 WINDOW OPTION REGISTER Register CIWDOFST Address R/W 0x4D80_0004 RW Description Reset Value Window offset register 0 SourceHsize Source Vsize Original Input TargetHsize_xx 3 TargetVsize_xx 1 2 Window Cut 4 1 , 2 : WinHorOfst,WinHorOfst2 = 3 , 4 : WinVerOfst,WinVerOfst2 TargetHsize_xx TargetHsize_Co or TargetHsize_Pr Figure 23-14.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR NOTE: Clear bits should be set by zero after clearing the flags. It should be as (WinHorOfst + WinHorOfst2) >= (SourceHsize – 720 * PreHorRatio_Pr) Crop Hsize ( = SourceHsize – WinHorOfst - WinHorOfst2) must be 4’s multiple of PreHorRatio. Crop Vsize ( = SourceVsize – WinVerOfst - WinVerOfst2) must be multiple of PreVerRatio when scale down.
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.3 GLOBAL CONTROL REGISTER Register CIGCTRL CIGCTRL Address R/W 0x4D80_0008 RW Bit Description Reset Value Global control register Description 2000_0000 Initial State Change State [31] Camera interface software reset. Before setting this bit, you should set the ITU601_656n bit of CISRCFMT as “1” temporarily at first SFR setting. Next sequence is recommended.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR Overflow (preview) IRQ_Cl_p IRQ_Ovfen IRQ_p Overflow (codec) IRQ_Cl_c IRQ_c Figure 23-15.
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.4 WINDOW OPTION REGISTER 2 Register CIDOWSFT2 CIWDOFST2 Reserved Address R/W 0x4D80_0014 RW Description Window offset register 2 Bit Description [31:27] [26:16] WinHorOfst2 Reset Value Window horizontal offset2 by pixel unit. (It should be 2’s multiple) 0 Initial State Change State 0 X 0 O 0 X 0 O Caution : SourceHsize-WinHorOfst- WinHorOfst2 should be 8’s multiple.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.7 Y3 START ADDRESS REGISTER Register CICOYSA3 CICOYSA3 Address R/W 0x4D80_0020 RW Description 3rd frame start address for codec DMA Bit [31:0] CICOYSA3 Reset Value Description Output format : YCbCr 4:2:2 or 4:2:0 address Output format : RGB 16/24 bit address Y 3rd frame start 0 Initial State Change State 0 X RGB 3rd frame start 6.
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.10 CB2 START ADDRESS REGISTER Register CICOCBSA2 CICOCBSA2 CICOCBSA2 Address R/W 0x4D80_002C RW Description Cb 2nd frame start address for codec DMA Bit [31:0] Reset Value Description Cb 2nd frame start address for codec DMA 0 Initial State Change State 0 X 6.
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CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.14 CR2 START ADDRESS REGISTER Register CICOCRSA2 CICOCRSA2 CICOCRSA2 Address R/W 0x4D80_003C RW Description Cr 2nd frame start address for codec DMA Bit [31:0] Reset Value Description Cr 2nd frame start address for codec DMA 0 Initial State Change State 0 X 6.
PAGE 647
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.17 CODEC TARGET FORMAT REGISTER Register CICOTRGFMT CICOTRGFMT Address R/W 0x4D80_0048 RW Description Target image format of codec DMA Bit [31] Reset Value Description 1 = YCbCr 4:2:2 codec scaler input image format. 0 Initial State Change State 0 O 0 O 0 O 0 = YCbCr 4:2:0 codec scaler input image format. In this case, horizontal line decimation is performed before codec scaler.
PAGE 648
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR X-axis flip Original image Y-axis flip 180' rotation Figure 23-16.
PAGE 649
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.
PAGE 650
CAMERA INTERFACE • S3C2450X RISC MICROPROCESSOR Non-Interleaved burst length Y Main burst length = 4, 8, 16 Remained burst length = 4, 8, 16 C Main burst length = 2, 4, 8, 16 Remained burst length = 2, 4, 8, 16 NOTE: When Interleave_Co = 1, there are some restricts in burst length setting as below. Burst size calculations are done to determine the wanted burst length. After finding the wanted burst length.
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S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE SourceHsize SourceVsize Scale Down TargetHsize_xx = TargetHsize_Co or TargetHsize_Pr DST_Width = TargetHsize_xx DST_Height = TargetVsize_xx SRC_Width = SourceHsize SRC_Height = SourceVsize SourceVsize Zoom In 3 2 1 4 1 2 : WinHorOfst, WinHorOfst2 3 4 : WinVerOfst, WinVerOfst2 TargetVsize_xx TargetHsize_xx SourceHsize Original Input TargetVsize_xx TargetHsize_xx Original Input TargetHsize_xx = TargetHsize_Co or TargetHsize_Pr DST_Width = T
PAGE 652
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR If ( SRC_Height >= 64 × DST_Height ) { Exit(-1); /* Out Of Vertical Scale Range */ } else if (SRC_Height >= 32 × DST_Height) { PreVerRatio_xx = 32; V_Shift = 5; } else if (SRC_Height >= 16 × DST_Height) { PreVerRatio_xx = 16; V_Shift = 4; } else if (SRC_Height >= 8 × DST_Height) { PreVerRatio_xx = 8; V_Shift = 3; } else if (SRC_Height >= 4 × DST_Height) { PreVerRatio_xx = 4; V_Shift = 2; } else if (SRC_Height >= 2 × DST_Height) { PreVerRatio_xx = 2; V_Shift =
PAGE 653
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.20 CODEC PRE-SCALER CONTROL REGISTER 1 Register CICOSCPRERATIO CICOSCPRERATIO Address R/W 0x4D80_0050 RW Description Codec pre-scaler ratio control Bit SHfactor_Co [31:28] Reserved [27:23] PreHorRatio_Co [22:16] Reserved [15:7] PreVerRatio_Co [6:0] Reset Value Description Shift factor for codec pre-scaler Horizontal ratio of codec pre-scaler Vertical ratio of codec pre-scaler 0 Initial State Change State 0 O 0 X 0 O 0 X 0 O 6.
PAGE 654
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.22 CODEC MAIN-SCALER CONTROL REGISTER Register CICOSCCTRL CICOSCCTRL Address R/W 0x4D80_0058 RW ScaleUp_V_Co 0 Initial State Change State Codec scaler bypass for upper 2048 x 2048 size (In this case, ImgCptEn_CoSC and ImgCptEn_PrSC should be 0, but ImgCptEn should be 1. It is not allowed to capturing preview image.
PAGE 655
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.24 CODEC STATUS REGISTER Register CICOSTATUS CICOSTATUS Address R/W 0x4D80_0064 R Bit Description Reset Value Codec path status 0 Description Initial State Change State OvFiY_Co [31] Overflow state of codec FIFO Y 0 X OvFiCb_Co [30] Overflow state of codec FIFO Cb 0 X OvFiCr_Co [29] Overflow state of codec FIFO Cr 0 X [28] Camera VSYNC (This bit can be referred by CPU for first SFR setting after external camera muxing.
PAGE 656
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.26 RGB2 START ADDRESS REGISTER Register CIPRCLRSA2 Address R/W 0x4D80_0070 RW CIPRCLRSA2 Bit CIPRCLRSA2 (v) [31:0] Description Reset Value RGB 2nd frame start address for preview DMA Description RGB 2nd frame start address for preview DMA 0 Initial State Change State 0 X 6.
PAGE 657
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.29 PREVIEW TARGET FORMAT REGISTER Register CIPRTRGFMT Address R/W 0x4D80_007C RW Description Reset Value Target image format of preview DMA 0x8000_0000 X-axis flip Original image Y-axis flip 180' rotation Figure 23-18.
PAGE 658
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.
PAGE 659
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.
PAGE 660
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.33 PREVIEW MAIN-SCALER CONTROL REGISTER Register CIPRSCCTRL CIPRSCCTRL Address R/W 0x4D80_008C RW Description Reset Value Preview main-scaler control Bit Description 0 Initial State Change State Sample_Pr (v) [31] Sampling method for format conversion.
PAGE 661
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.
PAGE 662
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.36 IMAGE CAPTURE ENABLE REGISTER Register CIIMGCPT CIIMGCPT Address R/W 0x4D80_00A0 RW Bit Description Reset Value Image capture enable command Description 0 Initial State Change State ImgCptEn [31] camera interface global capture enable 0 O ImgCptEn_ CoSc [30] capture enable for codec scaler. This bit must be zero in scaler-bypass mode. 0 O [29] capture enable for preview scaler.
PAGE 663
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.37 CODEC CAPTURE SEQUENCE REGISTER Register CICOCPTSEQ Address R/W 0x4D80_00A4 RW CICOCPTSEQ Bit Cpt_CoDMA_Seq [31:0] Description Reset Value Codec DMA capture sequence related 0xFFFFFFFF Description Initial State Capture sequence pattern in Codec DMA 0xFFFF_FFFF Cpt_CoDMA_Ptr 31 30 29 1 1 0 Capture Capture Cpt_CoDMA_Seq[31:0] ...... No Capture 1 1 0 0 1 Capture Repeat Figure 23-19.
PAGE 664
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.38 CODEC SCAN LINE OFFSET REGISTER Register CICOSCYOS CICOSCYOS Reserved Address R/W 0x4D80_00A8 RW Description [31:29] The number of the skipped pixels for initial offset (should be even number for word boundary alignment). This value must be set to 0 when scanline offset is not used. And, scanline offset can be used only when Interleave_Co is set to 1.
PAGE 665
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE SCREEN Initial offset Line offset Target image Figure 23-20.
PAGE 666
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.
PAGE 667
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.41 MSDMA Y START ADDRESS REGISTER Register CIMSYSA CIMSYSA Reserved CIMSYSA (v) Address R/W 0x4D80_00B4 RW Description MSDMA Y start address related Bit Description [31] [30:0] Reset Value DMA start address for Y component (YCbCr 4:2:0) DMA start address for YCbCr component (interleave 4:2:2) 0000_0000 Initial State Change State 0 X 0 X 6.
PAGE 668
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.44 MSDMA Y END ADDRESS REGISTER Register CIMSYEND CIMSYEND Reserved CIMSYEND (v) Address R/W Description 0x4D80_00C0 RW MSDMA Y end address related Bit Description [31] [30:0] DMA End address for Y component (YCbCr 4:2:0) DMA End address for YCbCr component (interleave 4:2:2) Reset Value 0000_0000 Initial State Change State 0 X 0 X 6.
PAGE 669
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.47 MSDMA Y OFFSET REGISTER Register CIMSYOFF CIMSYOFF Address R/W 0x4D80_00CC RW Description MSDMA Y offset related Bit Reserved [31:24] CIMSYOFF (v) [23:0] Reset Value Description Offset of Y component for fetching source image 0000_0000 Initial State Change State 0 X 0 X 6.
PAGE 670
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR 6.50.1 - MSDMA Start address Start address of ADDRStart_Y/Cb/Cr points the first word address where the corresponding component of Y/Cb/Cr is read. Each one should be aligned with word boundary (i.e. ADDRStart_X[1:0] = 00). ADDRStart_Cb and ADDRStart_Cr are valid only for the YCbCr420 source image format. 6.50.
PAGE 671
S3C2450X RISC MICROPROCESSOR CAMERA INTERFACE 6.51 MSDMA CONTROL REGISTER Register CIMSCTRL CIMSCTRL Reserved Address R/W 0x4D80_00D C RW Description MSDMA control register Bit Description [31:7] [6] EOF_MS Reset Value MSDMA read the saved memory data. 0000_0000 Initial State Chang e State 0 X 0 X 0 X 0 X 0 X 0 X 0 X When this operation done, EOF will be generated.
PAGE 672
CAMERA INTERFACE S3C2450X RISC MICROPROCESSOR start start 0 ->1 setting 1 -> 0 setting 0 -> 1 setting ENVID_MS Figure 23-22. ENVID_MS SFR setting when DMA start to Read Memory Data RGB start address, Preview Target format, Preview DMA Control etc.. MSDMA Start,End,OFFSET, MSDMA Source image width, MSDMA control SFR SFR Memory MSDMA Operation Done = EOF signal generation Scaler Preview DMA Operation Done = IRQ signal generation Figure 23-23.
PAGE 673
S3C2450X RISC MICROPROCESSOR 24 ADC AND TOUCH SCREEN INTERFACE ADC & TOUCH SCREEN INTERFACE 1 OVERVIEW The 12-bit CMOS ADC (Analog to Digital Converter) is a recycling type device with 10-channel analog inputs. It converts the analog input signal into 12-bit binary digital codes at a maximum conversion rate of 1MSPS with 5MHz A/D converter clock. A/D converter operates with on-chip sample-and-hold function and power down (standby) mode is supported.
PAGE 674
ADC AND TOUCH SCREEN INTERFACE S3C2450X RISC MICROPROCESSOR 2 ADC & TOUCH SCREEN INTERFACE OPERATION 2.1 BLOCK DIAGRAM Figure 24-1 shows the functional block diagram of A/D converter and touch screen interface. Note that the A/D converter device is a recycling type.
PAGE 675
S3C2450X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 2.2 FUNCTION DESCRIPTIONS 2.2.1 A/D Conversion Time When the PCLK frequency is 50 MHz, the prescaler value is 49 and total 10-bit and 12-bit conversion time is given: A/D converter freq. = 50 MHz/(49+1) = 1 MHz Conversion time = 1/(1MHz / (5cycles)) = 1/200 KHz = 5 us NOTE This A/D converter is designed to operate at maximum 5 MHz clock, so the conversion rate can go up to 1MSPS. 2.2.2 Touch Screen Interface Modes (AIN6 ~ AIN9) 1.
PAGE 676
ADC AND TOUCH SCREEN INTERFACE S3C2450X RISC MICROPROCESSOR 4. Waiting for interrupt mode (ADCTSC = 0xd3) Touch screen controller generates interrupt (INT_TC) signal when the stylus is down. The value of ADC touch screen control register (ADCTSC) is ‘0xd3’; PULL_UP is ‘0’, XP_SEN is ‘1’, XM_SEN is ‘0’, YP_SEN is ‘1’ and YM_SEN is ‘1’. Touch interrupt can be generated when stylus pen is down or up.
PAGE 677
S3C2450X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 3 ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS 3.1 ADC CONTROL (ADCCON) REGISTER Register ADCCON ADCCON ECFLG Address R/W 0x58000000 R/W Description ADC control register Bit [15] Description End of conversion flag (read only). Reset Value 0x3FC4 Initial State 0 0 = A/D conversion in process 1 = End of A/D conversion PRSCEN [14] A/D converter prescaler enable. 0 0 = Disable 1 = Enable PRSCVL [13:6] A/D converter prescaler value.
PAGE 678
ADC AND TOUCH SCREEN INTERFACE S3C2450X RISC MICROPROCESSOR 3.2 ADC TOUCH SCREEN CONTROL (ADCTSC) REGISTER Register ADCTSC ADCTSC UD_SEN Address R/W 0x58000004 R/W Description ADC touch screen control register Bit [8] Description Select interrupt source Stylus Up or Down Reset Value 0x058 Initial State 0 0 = Detect Stylus Down Signal. 1 = Detect Stylus Up Signal. YM_SEN [7] YM to GND Switch Enable 0 0 = Switch disable.(YM = AIN6, Hi-z) 1 = Switch enable.
PAGE 679
S3C2450X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 3.3 ADC START DELAY (ADCDLY) REGISTER Register ADCDLY ADCDLY DELAY Address R/W 0x58000008 R/W Bit [15:0] Description Reset Value ADC start or interval delay register 0x00ff Description Initial State Incase of ADC conversion mode (Normal, Separate, Auto conversion); ADC conversion is delayed by counting this value. Counting clock is PCLK.
PAGE 680
ADC AND TOUCH SCREEN INTERFACE S3C2450X RISC MICROPROCESSOR 3.4 ADC CONVERSION DATA (ADCDAT0) REGISTER Register ADCDAT0 ADCDAT0 UPDOWN Address R/W 0x5800000C R Description ADC conversion data register Bit [15] Description Up or down state of Stylus at Waiting for Interrupt Mode. Reset Value Initial State - 0 = Stylus down state 1 = Stylus up state AUTO_PST [14] Automatic sequencing conversion of X-position and Y-position.
PAGE 681
S3C2450X RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 3.5 ADC CONVERSION DATA (ADCDAT1) REGISTER Register ADCDAT1 ADCDAT1 UPDOWN Address R/W 0x58000010 R Description ADC conversion data register Bit [15] Description Up or down state of Stylus at Waiting for Interrupt Mode. Reset Value Initial State - 0 = Stylus down state 1 = Stylus up state AUTO_PST [14] Automatic sequencing conversion of X-position and Y-position.
PAGE 682
ADC AND TOUCH SCREEN INTERFACE S3C2450X RISC MICROPROCESSOR 3.7 ADC CHANNEL MUX REGISTER (ADCMUX) Register ADCMUX ADCMUX ADCMUX Address R/W 0x5800018 R/W Bit [3:0] Description Analog input channel select Description Analog input channel select.
PAGE 683
S3C2450X RISC MICROPROCESSOR 25 IIS-BUS INTERFACE IIS-BUS INTERFACE 1 OVERVIEW IIS (Inter-IC Sound) is one of the popular digital audio interface. The bus has only to handle audio data, while the other signals, such as sub-coding and control, are transferred separately. Surely, it is possible to transmit data between two IIS bus.
PAGE 684
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 4 BLOCK DIAGRAM Register File Figure 25-1. IIS-Bus Block Diagram 5 FUNCTIONAL DESCRIPTIONS IIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel control block as shown in Figure 25-1. Note that each FIFO has 32-bit width and 16 depth structure, which contains left/right channel data. So, FIFO access and data transfer are handled with left/right pair unit.
PAGE 685
S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE 5.1 MASTER/SLAVE MODE Master or slave mode can be chosen by setting IMS bit of IISMOD register. In master mode, I2SSCLK and I2SLRCLK are generated internally and supplied to external device. Therefore a root clock is needed for generating I2SSCLK and I2SLRzCLK by dividing.
PAGE 686
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 5.1.1 DMA Transfer In the DMA transfer mode, the transmitter or receiver FIFO are accessible by DMA controller. DMA service request is activated internally by the transmitter or receiver FIFO state. The FTXEMPT, FRXEMPT, FTXFULL, and FRXFULL bits of I2SCON register represent the transmitter or receiver FIFO data state.
PAGE 687
S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE 6 AUDIO SERIAL DATA FORMAT 6.1 IIS-BUS FORMAT The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO, left/right channel select clock I2SLRCLK, and serial bit clock I2SSCLK; the device generating I2SLRCLK and I2SSCLK is the master. Serial data is transmitted in 2's complement with the MSB first with a fixed position, whereas the position of the LSB depends on the word length.
PAGE 688
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR Figure 25-3 shows the audio serial format of IIS, MSB-justified, and LSB-justified. Note that in this figure, the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK (BFS is 48 fs, where fs is sampling frequency; I2SLRCLK frequency). Figure 25-3.
PAGE 689
S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE 6.4 SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (RCLK) can be selected by sampling frequency as shown in Table 25-1. Because RCLK is made by IIS pre-scaler, the pre-scaler value and RCLK type (256fs or 384fs or 512fs or 768fs) should be determined properly. Table 25-1. CODEC clock (CODECLK = 256fs, 384fs, 512fs, 768fs) IISLRCK (fs) 8.000 kHz 11.025 kHz 16.000 kHz 22.050 kHz 32.000 kHz 44.100 kHz 48.000 kHz 64.000 kHz 88.200 kHz 96.
PAGE 690
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 7 PROGRAMMING GUIDE The IIS bus interface can be accessed either by the processor using programmed I/O instructions or by the DMA controller. 7.1 INITIALIZATION 1. Before you use IIS bus interface, you have to configure GPIOs to IIS mode. And check signal’s direction. I2SLRCLK, I2SSCLK and I2SCDCLK is inout-type. The each of I2SSDI and I2SSDO is input and output. 2. Now then, you choose clock source. S3C2450 has four clock sources.
PAGE 691
S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE 7.4 EXAMPLE CODE TX CHANNEL The I2S TX channel provides a single stereo compliant output. The transmit channel can operate in master or Slave mode. Data is transferred between the processor and the I2S controller via an APB access or a DMA access. The processor must write words in multiples of two (i.e. for left and right audio sample).The words are serially shifted out timed with respect to the audio serial bitclk, SCLK and word select clock, LRCLK.
PAGE 692
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR The Data is aligned in the TX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 31 23 RIGHT CHANNEL 16 15 7 LEFT CHANNEL 0 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 25-4.
PAGE 693
S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE The Data is aligned in the TX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) 31 23 INVALID INVALID INVALID INVALID 0 LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 25-5.
PAGE 694
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR RX CHANNEL The I2S RX channel provides a single stereo compliant output. The receive channel can operate in master or slave mode. Data is received from the input line and transferred into the RX FIFO. The processor can then read this data via an APB read or a DMA access can access this data. RX Channel has a 16X32 bit wide RX FIFO where the processor or DMA can read upto 16 left/right data samples after enabling the channel for reception.
PAGE 695
S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE The Data is aligned in the RX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 31 23 RIGHT CHANNEL 16 15 7 LEFT CHANNEL 0 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 25-6.
PAGE 696
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR The Data is aligned in the RX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) 31 23 0 INVALID LEFT CHANNEL LOC 0 INVALID RIGHT CHANNEL LOC 1 INVALID LEFT CHANNEL LOC 2 INVALID RIGHT CHANNEL LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 25-7. RX FIF0 Structure for BLC = 10 (24-bits/channel) The RXCHPAUSE in the I2SCON register can stop the serial data reception on the I2SSDI.
PAGE 697
S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE 8 IIS-BUS INTERFACE SPECIAL REGISTERS Table 25-3.
PAGE 698
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 8.1 IIS CONTROL REGISTER (IISCON) Register Address IISCON 0x55000100 IISCON Bit R/W [31:18] R/W Reserved. Program to zero. [17] R/W TX FIFO under-run interrupt status. And this is used by interrupt clear bit. When this is high, you can do interrupt clear by writing ‘1’. FTXURSTATUS Description IIS interface control register Reset Value 0x0000_0600 Description 0 = Interrupt didn’t be occurred. 1 = Interrupt was occurred.
PAGE 699
S3C2450X RISC MICROPROCESSOR IISCON RXDMAPAUSE Bit R/W [5] R/W IIS-BUS INTERFACE Description Rx DMA operation pause command. Note that when this bit is activated at any time, the DMA request will be halted after current on-going DMA transfer is completed. 0 = No pause DMA operation 1 = Pause DMA operation TXCHPAUSE [4] R/W Tx channel operation pause command. Note that when this bit is activated at any time, the channel operation will be halted after left-right channel data transfer is completed.
PAGE 700
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 8.2 IIS MODE REGISTER (IISMOD) Register Address IISMOD 0x55000104 IISMOD Bit R/W [31:15] R/W Reserved. Program to zero.
PAGE 701
S3C2450X RISC MICROPROCESSOR IISMOD RFS Bit R/W [4:3] R/W IIS-BUS INTERFACE Description IIS root clock (codec clock) frequency select. 00 = 256 fs, where fs is sampling frequency 01 = 512 fs 10 = 384 fs 11 = 768 fs (Even in the slave mode, this bit should be set for correct) BFS [2:1] R/W Bit clock frequency select. 00 = 32 fs, where fs is sampling frequency 01 = 48 fs 10 = 16 fs 11 = 24 fs (Even in the slave mode, this bit should be set for correct) [0] R/W Reserved. Program to zero.
PAGE 702
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR 8.3 IIS FIFO CONTROL REGISTER (IISFIC) Register Address IISFIC 0x55000108 IISFIC Bit R/W [31:16] R/W Reserved. Program to zero. [15] R/W TX FIFO flush command. TFLUSH Description Reset Value IIS interface FIFO control register 0x0000_0000 Description 0 = No flush 1 = Flush [14:13] R/W Reserved. Program to zero. FTXCNT [12:8] R TX FIFO data count. (0~16) RFLUSH [7] R/W RX FIFO flush command.
PAGE 703
S3C2450X RISC MICROPROCESSOR IIS-BUS INTERFACE 8.5 IIS TRANSMIT REGISTER (IISTXD) Register Address IISTXD 0x55000110 IISTXD Bit R/W [31:0] W IISTXD Description Reset Value IIS interface transmit data register 0x0000_0000 Description TX FIFO write data. Note that the left/right channel data is allocated as the following bit fields. R[23:0], L[23:0] when 24-bit BLC R[31:16], L[15:0] when 16-bit BLC R[23:16], L[7:0] when 8-bit BLC 8.
PAGE 704
IIS-BUS INTERFACE S3C2450X RISC MICROPROCESSOR NOTES 25-22
PAGE 705
S3C2450X RISC MICROPROCESSOR 26 IIS MULTI AUDIO INTERFACE IIS MULTI AUDIO INTERFACE 1 OVERVIEW IIS (Inter-IC Sound) is one of the popular digital audio interface. The bus has only to handle audio data, while the other signals, such as sub-coding and control, are transferred separately. Surely, it is possible to transmit data between two IIS bus.
PAGE 706
S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR 4 BLOCK DIAGRAM Figure 26-1. IIS-Bus Block Diagram 5 FUNCTIONAL DESCRIPTIONS IIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel control block as shown in Figure 26-1. Note that each FIFO has 32-bit width and 16 depth structure, which contains left/right channel data. So, FIFO access and data transfer are handled with left/right pair unit.
PAGE 707
S3C2450X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 5.1 MASTER/SLAVE MODE Master or slave mode can be chosen by setting IMS bit of IISMOD register. In master mode, I2SSCLK and I2SLRCLK are generated internally and supplied to external device. Therefore a root clock is needed for generating I2SSCLK and I2SLRCLK by dividing.
PAGE 708
S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR 5.2 DMA TRANSFER In the DMA transfer mode, the transmitter or receiver FIFO are accessible by DMA controller. DMA service request is activated internally by the transmitter or receiver FIFO state. The FTXEMPT, FRXEMPT, FTXFULL, and FRXFULL bits of I2SCON register represent the transmitter or receiver FIFO data state.
PAGE 709
S3C2450X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 6 AUDIO SERIAL DATA FORMAT 6.1 IIS-BUS FORMAT The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO, left/right channel select clock I2SLRCLK, and serial bit clock I2SSCLK; the device generating I2SLRCLK and I2SSCLK is the master. Serial data is transmitted in 2's complement with the MSB first with a fixed position, whereas the position of the LSB depends on the word length.
PAGE 710
S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR Figure 26-3 shows the audio serial format of IIS, MSB-justified, and LSB-justified. Note that in this figure, the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK (BFS is 48 fs, where fs is sampling frequency; I2SLRCLK frequency). Figure 26-3.
PAGE 711
S3C2450X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 6.4 SAMPLING FREQUENCY AND MASTER CLOCK Master clock frequency (RCLK) can be selected by sampling frequency as shown in Table 26-1. Because RCLK is made by IIS pre-scaler, the pre-scaler value and RCLK type (256fs or 384fs or 512fs or 768fs) should be determined properly. Table 26-1. CODEC clock (CODECLK = 256fs, 384fs, 512fs, 768fs) IISLRCK (fs) 8.000 kHz 11.025 kHz 16.000 kHz 22.050 kHz 32.000 kHz 44.100 kHz 48.000 kHz 64.000 kHz 88.
PAGE 712
S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR 7 PROGRAMMING GUIDE The IIS bus interface can be accessed either by the processor using programmed I/O instructions or by the DMA controller. 7.1 INITIALIZATION 1. Before you use IIS bus interface, you have to configure GPIOs to IIS mode. And check signal’s direction. I2SLRCLK, I2SSCLK and I2SCDCLK is inout-type. The each of I2SSDI and I2SSDO is input and output. 2. Now then, you choose clock source. S3C2450 has four clock sources.
PAGE 713
S3C2450X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 7.4 EXAMPLE CODE TX CHANNEL The I2S TX channel provides single/double/tripple stereo compliant outputs. The transmit channel can operate in master or Slave mode. Data is transferred between the processor and the I2S controller via an APB access or a DMA access. The processor must write words in multiples of two (i.e. for left and right audio sample).
PAGE 714
S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR The Data is aligned in the TX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 31 23 RIGHT CHANNEL 16 15 7 LEFT CHANNEL 0 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 26-4.
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S3C2450X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE The Data is aligned in the TX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) 31 23 0 INVALID LEFT CHANNEL LOC 0 INVALID RIGHT CHANNEL LOC 1 INVALID LEFT CHANNEL LOC 2 INVALID RIGHT CHANNEL LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 26-5.
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S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR RX CHANNEL The I2S RX channel provides a single stereo compliant output. The receive channel can operate in master or slave mode. Data is received from the input line and transferred into the RX FIFO. The processor can then read this data via an APB read or a DMA access can access this data. RX Channel has a 16X32 bit wide RX FIFO where the processor or DMA can read UPTO 16 left/right data samples after enabling the channel for reception.
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S3C2450X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE The Data is aligned in the RX FIFO for 8-bits/channel or 16-bits/channel BLC as shown BLC=00 BLC=00 BLC=01 BLC=01 31 23 RIGHT CHANNEL 16 15 7 LEFT CHANNEL 0 LOC 0 LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 26-6.
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S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR The Data is aligned in the RX FIFO for 24-bits/channel BLC as shown BLC = 10 (24-bits/channel) 31 23 0 INVALID LEFT CHANNEL LOC 0 INVALID RIGHT CHANNEL LOC 1 INVALID LEFT CHANNEL LOC 2 INVALID RIGHT CHANNEL LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 26-7.
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S3C2450X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 8 IIS-BUS INTERFACE SPECIAL REGISTERS Table 26-3.
PAGE 720
S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR 8.1 IIS CONTROL REGISTER (IISCON) Register Address Description IISCON 0x55000000 IISCON Bit R/W Reserved [31:18] R/W Reserved. Program to zero. FTXURSTATUS [17] R/W TX FIFO under-run interrupt status. And this is used by interrupt clear bit. When this is high, you can do interrupt clear by writing ‘1’. IIS interface control register Reset Value 0x0000_C600 Description 0 = Interrupt didn’t be occurred. 1 = Interrupt was occurred.
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S3C2450X RISC MICROPROCESSOR IISCON Bit R/W FRXFULL [7] R IIS MULTI AUDIO INTERFACE Description Rx FIFO full status indication. 0 = FIFO is not full (ready for receive data from channel) 1 = FIFO is full (not ready for receive data from channel) TXDMAPAUSE [6] R/W Tx DMA operation pause command. Note that when this bit is activated at any time, the DMA request will be halted after current on-going DMA transfer is completed.
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S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR 8.2 IIS MODE REGISTER (IISMOD) Register Address Description IISMOD 0x55000004 IISMOD Bit R/W Reserved [31:15] R/W Reserved. Program to zero. CDD2 [21:20] R/W Channel-2 Data Discard. Discard means zero padding. It only supports 8/16 bit mode. IIS interface mode register Reset Value 0x0000_0000 Description 00 = No Discard 01 = I2STXD[15:0] Discard 10 = I2STXD[31:16] Discard 11 = Reserved CDD1 [19:18] R/W Channel-1 Data Discard.
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S3C2450X RISC MICROPROCESSOR IISMOD Bit R/W TXR [9:8] R/W IIS MULTI AUDIO INTERFACE Description Transmit or receive mode select. 00 = Transmit only mode 01 = Receive only mode 10 = Transmit and receive simultaneous mode 11 = Reserved LRP [7] R/W Left/Right channel clock polarity select. 0 = Low for left channel and high for right channel 1 = High for left channel and low for right channel SDF [6:5] R/W Serial data format.
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S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR 8.3 IIS FIFO CONTROL REGISTER (IISFIC) Register Address IISFIC 0x55000008 IISFIC Bit R/W [31:29] R/W [28:24] R [23:21] R/W Reserved. Program to zero. FTX1CNT [20:16] R TX FIFO1 data count. (0~16) TFLUSH [15] R/W FTX2CNT Description IIS interface FIFO control register Reset Value 0x0000_0000 Description Reserved. Program to zero. TX FIFO2 data count. (0 ~ 16) TX FIFO flush command.
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S3C2450X RISC MICROPROCESSOR IIS MULTI AUDIO INTERFACE 8.5 IIS TRANSMIT REGISTER (IISTXD) Register Address Description IISTXD 0x55000010 IISTXD Bit R/W Description IISTXD [31:0] W TX FIFO write data. Note that the left/right channel data is allocated as the following bit fields. IIS interface transmit data register Reset Value 0x0000_0000 R[23:0], L[23:0] when 24-bit BLC R[31:16], L[15:0] when 16-bit BLC R[23:16], L[7:0] when 8-bit BLC 8.
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S3C2450X RISC MICROPROCESSOR S3C2450X RISC MICROPROCESSOR NOTES 26-22
PAGE 727
S3C2450X RISC MICROPROCESSOR 27 AC97 CONTROLLER AC97 CONTROLLER 1 OVERVIEW The AC97 Controller Unit of the S3C2450 supports the AC97 revision 2.0 features. AC97 Controller communicates with AC97 Codec using audio controller link (AC-link). Controller sends the stereo PCM data to Codec. The external digital-to-analog converter (DAC) in the Codec then converts the audio sample to an analog audio waveform.
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AC97 CONTROLLER S3C2450X RISC MICROPROCESSOR 2 AC97 CONTROLLER OPERATION This section explains the AC97 controller operation. Also it says to program guide. You must study AC-Link, Power-down sequence and Wake-up sequence. 2.1 BLOCK DIAGRAM Figure 27-1 shows the functional block diagram of S3C2450 AC97 Controller. The AC97 signals form the AC-link, which is a point-to-point synchronous serial inter-connecting that supports full-duplex data transfers.
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S3C2450X RISC MICROPROCESSOR AC97 CONTROLLER 2.2 INTERNAL DATA PATH Figure 27-2 shows the internal data path of S3C2450 AC97 Controller. It has stereo Pulse Code Modulated (PCM) In, Stereo PCM Out and mono Mic-in buffers, which consist of 16-bit, 16 entries buffer. It also has 20-bit I/O shift register via AC-link.
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AC97 CONTROLLER S3C2450X RISC MICROPROCESSOR 3 OPERATION FLOW CHART When you initialize the AC97 controller, you must assert system reset or cold reset. Because we don’t know the previous state of the external the AC97 audio-codec. This assumes that GPIO is already ready. Then you make codec ready interrupt enable. You can check codec ready interrupt by polling or interrupt. When interrupt is occurred, you must de-assert codec ready interrupt.
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S3C2450X RISC MICROPROCESSOR AC97 CONTROLLER 4 AC-LINK DIGITAL INTERFACE PROTOCOL Each AC97 Codec incorporates a five-pin digital serial interface that links it to the S3C2450 AC97 Controller. AClink is a full-duplex, fixed-clock, PCM digital stream. It employs a time division multiplexed (TDM) scheme to handle control register accesses and multiple input and output audio streams. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams.
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AC97 CONTROLLER S3C2450X RISC MICROPROCESSOR 4.1 AC-LINK OUTPUT FRAME (SDATA_OUT) Slot 0: Tag Phase In slot 0, the first bit is a bit (SDATA_OUT, bit 15) which represents the validity of the entire frame. If bit 15 is a 1, the current frame contains at least a valid time slot. The next 12 bit positions correspond each 12 time slot contains valid data. Bits 0 and 1 of slot 0 are used as CODEC IO bits for I/O reads and writes to the CODEC registers as described in the next section.
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S3C2450X RISC MICROPROCESSOR AC97 CONTROLLER 4.2 AC-LINK INPUT FRAME (SDATA_IN) Slot 0: Tag Phase In slot 0, the first bit is a bit (SDATA_OUT, bit 15) that indicates whether the AC97 controller is in the CODEC ready state. If the CODEC Ready bit is a 0, the AC97 controller is not ready for normal operation. This condition is normal after the power is de-asserted on reset and the AC97 controller voltage references are settling.
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AC97 CONTROLLER S3C2450X RISC MICROPROCESSOR Slot 4: PCM Right channel audio Slot 4 which is audio input frame is the right channel audio output of the AC97 Codec. If a sample has a resolution that is less than 16 bits, the AC97 Codec fills all training non-valid bit positions in the slot with zeroes. Slot 6: Microphone Record Data The AC97 Controller only supports 16-bit resolution for the MIC-in channel.
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S3C2450X RISC MICROPROCESSOR AC97 CONTROLLER 5 AC97 POWER-DOWN For details, please refer the AC-Link Power Managerment part of AC97 revision 2.0 specification. SYNC BIT_CLK SDATA_OUT slot 12 prev.frame TAG SDATA_IN slot 12 prev.frame TAG Write to 0X26 Data PR4 Figure 27-7. AC97 Power-down Timing 5.1.1 Powering Down the AC-link The AC-link signals enter a low power mode when the AC97 Codec Power-down register (0x26) bit PR4 is set to a 1 (by writing 0x1000).
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AC97 CONTROLLER S3C2450X RISC MICROPROCESSOR 6 CODEC RESET For details, please refer the CODEC Reset part of AC97 revision 2.0 specification. 6.1.1 Cold AC97 Reset A cold reset is generated when the nRESET pin is asserted through the AC_GLBCTRL. Asserting and deasserting nRESET activates BITCLK and SDATA_OUT. All AC97 control registers are initialized to their default power on reset values. nRESET is an asynchronous AC97 input. 6.1.
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S3C2450X RISC MICROPROCESSOR AC97 CONTROLLER 7 AC97 CONTROLLER STATE DIAGRAM 9 8 WARM IDLE 1 9 9 7 9 INIT 5 6 ACTIVE 9 LP 4 2 READY 3 1 : PCLK rising 2 : ACLINK_ON 3 : CODEC_READY & TRANS_DATA & NORMAL_SYNC 4 : ~CODEC_READY | ~TRANS_DATA 5 : !ACLINK_ON 6 : POWER_DOWN 7 : WARM_RESET 8 : CODEC_WAKEUP 9 : COLD_RESET | ~PRESETn Figure 27-9. AC97 State Diagram This is the state diagram of AC97 controller. It is helpful to understand AC97 controller state machine.
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AC97 CONTROLLER S3C2450X RISC MICROPROCESSOR 8 AC97 CONTROLLER SPECIAL REGISTERS 8.
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S3C2450X RISC MICROPROCESSOR AC97 CONTROLLER 8.2 AC97 GLOBAL CONTROL REGISTER (AC_GLBCTRL) This is the global register of the AC97 controller. There are interrupt control registers, DMA control registers, ACLink control register, data transmission control register and related reset control register.
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AC97 CONTROLLER S3C2450X RISC MICROPROCESSOR 8.3 AC97 GLOBAL STATUS REGISTER (AC_GLBSTAT) This is the status register. When the interrupt is occurred, you can check what the interrupt source is. Register AC_GLBSTAT Address R/W 0x5B000004 R AC_GLBSTAT Description AC97 Global Status Register Bit - Description [22] PCM out channel underrun interrupt [21] PCM in channel overrun interrupt 0x00000001 Initial State [31:23] Reserved.
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S3C2450X RISC MICROPROCESSOR AC97 CONTROLLER 8.5 AC97 CODEC STATUS REGISTER (AC_CODEC_STAT) If the Read enable bit is 1 and Codec command address is valid, Codec status data is also valid. Register AC_CODEC_STAT AC_CODEC_STAT Address R/W 0x5B00000C R Description AC97 Codec Status Register Bit Description Reset Value 0x00000000 Initial State - [31:23] Reserved.
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AC97 CONTROLLER S3C2450X RISC MICROPROCESSOR 8.7 AC97 MIC IN CHANNEL FIFO ADDRESS REGISTER (AC_MICADDR) To index the internal MIC-in FIFO address. Register AC_MICADDR AC_MICADDR Address R/W Description Reset Value 0x5B000014 R AC97 MIC In Channel FIFO Address Register 0x00000000 Bit Description Initial State - [31:20] Reserved. 0000 Read address [19:16] MIC in channel FIFO read address 0000 - [15:4] Reserved. 0x000 Write address [3:0] MIC in channel FIFO write address 0000 8.
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S3C2450X RISC MICROPROCESSOR 28 PCM AUDIO INTERFACE PCM AUDIO INTERFACE 1 OVERVIEW The S3C2450 has two ports of PCM Audio Interface. The PCM Audio Interface module provides PCM bidirectional serial interface to an external Codec. 1.1 FEATURE • Mono, 16bit PCM, 2 ports audio interface.
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PCM AUDIO INTERFACE S3C2450X RISC MICROPROCESSOR 2 PCM AUDIO INTERFACE The PCM Audio Interface provides a serial interface to an external Codec. The PCM module receives an input PCMSOURCE_CLK that is used to generate the serial shift timing. The PCM interface outputs a serial data out, a serial shift clock, and a sync signal. Data is received from the external Codec over a serial input line. All the serial data in, serial data out, and sync signal are synchronized to the serial shift clock.
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S3C2450X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3 PCM TIMING The following figures show the timing relationship for the PCM transfers. Figure 28-1 shows a PCM transfer with the MSB configured to be coincident with the PCMFSYNC. This MSB positioning corresponds to setting the TX_MSB_POS and RX_MSB_POS bits in PCMCTL register to be 0. input PCMSOURCE_CLK output PCMSCLK output PCMFSYNC output PCMSOUT 15 14 13 ... 1 0 dont care 15 14 input PCMSIN 15 14 13 ...
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PCM AUDIO INTERFACE S3C2450X RISC MICROPROCESSOR 3.1 PCM INPUT CLOCK DIAGRAM Figure 28-3. Input Clock Diagram for PCM S3C2450 PCM is able to select clock either PCLK or External Clock. Refer figure 28-3. To enable clock gating, please refer to the SYSCON part(SCLKCON, PCLKCON).
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S3C2450X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3.2 PCM REGISTERS There are 8 control registers for each PCM port. (Since there are two ports, the total number of control registers is 16.) The number(0 or 1) that follows each register name indicates which PCM module this register belongs to. The details of those registers are as follows. 3.
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PCM AUDIO INTERFACE S3C2450X RISC MICROPROCESSOR 3.4 PCM CONTROL REGISTER The PCM_CTL register is used to control the various aspects of the PCM module. It also provides a status bit to provide the option to using polling instead of interrupt based control.
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S3C2450X RISC MICROPROCESSOR PCM_CTLn Bit PCM AUDIO INTERFACE Description Initial State DMA_RX request will occur whenever the RXFIFO is not empty.
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PCM AUDIO INTERFACE S3C2450X RISC MICROPROCESSOR 3.5 PCM CLK CONTROL REGISTER Register Address R/W Description Reset Value PCM_CLKCTL0 0x5C000004 R/W Control the PCM0 Audio Inteface 0x00000000 PCM_CLKCTL1 0x5C000104 R/W Control the PCM1 Audio Inteface 0x00000000 The bit definitions for the PCM_CTL Control Register are shown below: PCM_CLKCTLn Reserved CTL_SERCLK_EN Bit [31:20] [19] Description Initial State Reserved Enable the serial clock division logic.
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S3C2450X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3.
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PCM AUDIO INTERFACE S3C2450X RISC MICROPROCESSOR 3.
PAGE 753
S3C2450X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3.8 PCM INTERRUPT CONTROL REGISTER The PCM_IRQ_CTL register is used to control the various aspects of the PCM interrupts.
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PCM AUDIO INTERFACE PCM_IRQ_CTLn TXFIFO_ERROR_ S3C2450X RISC MICROPROCESSOR Bit [7] STARVE Description Interrupt is generated for TxFIFO starve ERROR. Initial State 0 This occurs whenever the TxFIFO is read when it is still empty. This is considered an ERROR and will have unexpected results 1: IRQ source enabled 0: IRQ source disabled TXFIFO_ERROR_ [6] OVERFLOW Interrupt is generated for TxFIFO overflow ERROR. 0 This occurs whenever the TxFIFO is written when it is already full.
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S3C2450X RISC MICROPROCESSOR PCM_IRQ_CTLn RXFIFO_ERROR_ OVERFLOW PCM AUDIO INTERFACE Bit [0] Description Interrupt is generated for RxFIFO overflow ERROR. Initial State 0 This occurs whenever the RxFIFO is written when it is already full.
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PCM AUDIO INTERFACE S3C2450X RISC MICROPROCESSOR 3.9 PCM INTERRUPT STATUS REGISTER The PCM_IRQ_STAT register is used to report IRQ status. Register Address R/W Description Reset Value PCM_IRQ_STAT0 0x5C000014 R PCM0 Interrupt Status 0x00000000 PCM_IRQ_STAT1 0x5C000114 R PCM1 Interrupt Status 0x00000000 The bit definitions for the PCM_IRQ_STATUS Register are described below: PCM_IRQ_STATn Reserved IRQ_PENDING Bit Description Initial State [31:14] Reserved [13] Monitoring PCM IRQ.
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S3C2450X RISC MICROPROCESSOR PCM_IRQ_STATn TXFIFO_ERROR _OVERFLOW PCM AUDIO INTERFACE Bit Description Initial State [6] Interrupt is generated for TX FIFO overflow ERROR. This occurs whenever the TX FIFO is written when it is already full. This is considered as an ERROR and will have unexpected results 0 1 = IRQ is occurred. 0 = IRQ is not occurred. RXFIFO_EMPTY [5] Interrupt is generated whenever the RX FIFO is empty 1 = IRQ is occurred. 0 = IRQ is not occurred.
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PCM AUDIO INTERFACE S3C2450X RISC MICROPROCESSOR 3.10 PCM FIFO STATUS REGISTER The PCM_FIFO_STAT register is used to report FIFO status. Register Address R/W Description Reset Value PCM_FIFO_STAT0 0x5C000018 R PCM0 FIFO Status 0x00000000 PCM_FIFO_STAT1 0x5C000118 R PCM1 FIFO Status 0x00000000 The bit definitions for the PCM_FIFO_STATUS Register are shown below: PCM_FIFO_STATn Bit Description Initial State Reserved [31:20] Reserved TXFIFO_COUNT [19:14] TX FIFO data count(0 ~ 32).
PAGE 759
S3C2450X RISC MICROPROCESSOR PCM AUDIO INTERFACE 3.11 PCM INTERRUPT CLEAR REGISTER The PCM_CLRINT register is used to clear the interrupt. Interrupt service routine is responsible for clearing interrupt asserted. Writing any values on this register clears interrupts for ARM. Reading this register is not allowed. Clearing interrupt must be prior to resolving the interrupt condition, otherwise another interrupt that would occur after this interrupt may be ignored.
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PCM AUDIO INTERFACE S3C2450X RISC MICROPROCESSOR NOTES 28-18
PAGE 761
S3C2450X RISC MICROPROCESSOR 29 ELECTRICAL DATA ELECTRICAL DATA 1 ABSOLUTE MAXIMUM RATINGS Table 29-1. Absolute Maximum Rating Parameter Min Max VDDi, VDDiarm, VDDalive, VDDA_MPLL, VDDA_EPLL, VDDI_UDEV -0.5 1.8 VDD_OP1, VDD_OP2, VDD_OP3, VDD_RTC, VDD_SRAM, VDD_CAM, VDD_SD, VDDA_ADC, VDDA33x, VDD_USBOSC -0.5 4.6 VDD_SDRAM -0.5 3.6 DC Input Voltage VIN -0.5 3.6/4.8 DC Output Voltage VOUT -0.5 3.6/4.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR 2 RECOMMENDED OPERATING CONDITIONS Table 29-2. Recommended Operating Conditions (400MHz) Parameter Symbol DC Supply Voltage for Alive Block VDDalive DC Supply Voltage for Core Block ARMCLK / HCLK 400/133 MHz VDDiarm VDDi VDDA_MPLL VDDA_EPLL Min Typ Max 1.15 1.2 1.25 1.25 1.3 1.35 DC Supply Voltage for I/O Block1 VDD_OP1** 1.7 1.8 / 2.5 /3.3 3.6 DC Supply Voltage for I/O Block2 VDD_OP2 1.7 1.8 / 2.5 / 3.3 3.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-3. Recommended Operating Conditions (533MHz) Parameter Symbol Min Typ Max 1.15 1.2 1.25 VDDiarm 1.275 1.325 1.375 VDDi VDDA_MPLL VDDA_EPLL 1.15 1.2 1.25 DC Supply Voltage for Alive Block VDDalive DC Supply Voltage for Core Block ARMCLK / HCLK 533/133 MHz DC Supply Voltage for I/O Block1 VDD_OP1** 1.7 1.8 / 2.5 /3.3 3.6 DC Supply Voltage for I/O Block2 VDD_OP2 1.7 1.8 / 2.5 / 3.3 3.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR 3 D.C. ELECTRICAL CHARACTERISTICS Table 29-4. Normal I/O PAD DC Electrical Characteristics VDD = 1.7V~3.60V, Vext = 3.0~5.5V , TA = -40 to 85°C Parameter Condition Min Typ VDD Power Off Vtol Vih Vil ΔV Tolerant external voltage** VDD Power On Max Unit 3.6 V VDD=3.3V 5.5 VDD=2.5V 5.5 VDD=1.8V 3.6 V High Level Input Voltage LVCMOS Interface 0.7VDD VDD+0.3 V LVCMOS Interface -0.3 0.3VDD V Hysteresis Voltage 0.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-5. Special Memory DDR I/O PAD DC Electrical Characteristics VDD =1.7V~2.7V, Vext = 3.0~3.6V , TA = -40 to 85°C Parameter Condition Min Typ VDD Power Off Vtol Vih Vil ΔV Tolerant external voltage** VDD Power On Max Unit 2.7 V VDD=2.5V 3.6 VDD=1.8V 3.6 V High Level Input Voltage LVCMOS Interface 0.7VDD VDD+0.3 V LVCMOS Interface -0.3 0.3VDD V Hysteresis Voltage 0.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR Table 29-6. USB DC Electrical Characteristics VDD = 3.0 to 3.6V; GND = 0V; Cload = 2uF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 3.3 3.6 V VDD Supply voltage 3.0 VDI Differential input sensitivity 0.2 VCM Differential common mode voltage 0.8 VIL Low level input voltage VIH High level input voltage VOL Low level output voltage RL = 1.5KΩ to +3.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA 4 A.C. ELECTRICAL CHARACTERISTICS tXTALCYC 1/2 VDD_OP1 1/2 VDD_OP1 NOTE: The clock input from the X TIpll pin. Figure 29-1. XTIpll Clock Timing tEXTCYC tEXTLOW tEXTHIGH V IH 1/2 VDD_OP1 V IH 1/2 VDD_OP1 V IL V IL NOTE: The clock input from the EXTCLK pin. Figure 29-2. EXTCLK Clock Input Timing EXTCLK tEX2HC HCLK (internal) Figure 29-3.
PAGE 768
ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR HCLK (internal) tHC2CK CLKOUT (HCLK) tHC2SCLK SCLK Figure 29-4. HCLK/CLKOUT/SCLK in case that EXTCLK is used Figure 29-5.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Power PLL can operate after OM[3:2] is latched. nRESET XTIpll or EXTCLK ... PLL is configured by S/W first time. tPLL Clock Disable VCO is adapted to new clock frequency. VCO output ... tRST2RUN ... FCLK MCU operates by XTIpll or EXTCLK clcok. FCLK is new frequency. Figure 29-6.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR EXTCLK XTIpll Wake up from sleep mode Clock Disable tOSC2 VCO Output Several slow clocks (XTIpll or EXTCLK) FCLK Sleep mode is initiated. Figure 29-7.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Figure 29-8. SMC Synchronous Read Timing Figure 29-9.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR Asynchronous Write SMCLK tADDRD_A RADDR A tDOD_A D(A) RDATA tCSD_A nRCS nRWE tWED Figure 29-10. SMC Asynchronous Write Timing Figure 29-11.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA S M C LK RADDR [26 :0] A RDATA [31 :0] D (A ) nR C S nR O E nW A IT tW S tH S Figure 29-12.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR TACLS TWRPH0 TWRPH1 HCLK tCLED tCLED FCLE tWED tWED nFWE tWDD tWDD RDATA [15:0] COMMAND TACLS TWRPH0 TWRPH1 TACLS TWRPH0 TWRPH1 HCLK HCLK tALED tALED tALED tALED FALE FALE tWED tWED tWED tWED nFWE nFWE tWDD tWDD tWDD RDATA [15:0] RDATA [15:0] ADDRESS TWRPH0 tWDD ADDRESS TWRPH0 TWRPH1 HCLK TWRPH1 HCLK tWED tRED tWED nFWE tRED nFRE tWDD tRDS tWDD RDATA WDATA tRDH Figure 29-13.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Figure 29-14.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR SCLK tSCD WRITE TIMING @ RL = 3, WL=RL-1 nSCAS tSWD nSWE tDQSS DQS tWPRE SDATA tDS tDH READ TIMING @ RL = 3 nSCAS tSWD nSWE DQS tDQSQ SDATA Figure 29-15. DDR2 Timing Parameter Symbol Min Max Unit tDQSS 0.4 0.66 ns DDR2 DQ and DM output setup time tDS x 2.70 ns DDR2 DQ and DM output hold time tDH x 1.53 ns tDQSQ x 0.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA SCLK SCKE '1' tSAD tSAD SADDR tSAD A10/AP tSCSD tSCSD tSRD tSRD nSCSx nSRAS tSCD nSCAS DQMx '1' tSWD tSWD nSWE SDATA 'HZ' Figure 29-16.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR SCLK SCKE '1' tSAD tSAD SADDR tSAD A10/AP tSCSD tSCSD tSRD tSRD nSCSx nSRAS '1' Trp Trc tSCD nSCAS DQMx '1' tSWD nSWE SDATA 'HZ' NOTE: Before executing auto/self refresh command, all banks must be in idle state. Figure 29-17.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA HCLK tXRS nXDREQ tXRS tXAD tCADH nXDACK Min. 3SCLK Read Write tCADL Figure 29-18. External DMA Timing (Handshake, Single transfer) Tf2hsetup VSYNC Tf2hhold HSYNC Tvspw Tvfpd Tvbpd VDEN HSYNC Tl2csetup Tvclkh Tvclk VCLK Tvclkl Tvdhold VD Tvdsetup Tve2hold VDEN Figure 29-19.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR I2SLRCLK(Output) TLRId I2SSCLK(Output) TDS TDH I2SSDO(Output) Figure 29-20. IIS Interface Timing (I2S Master Mode Only) I2SLRCLK(Input) TLRId I2SSCLK(Input) TDS TDH I2SSDI(Input) Figure 29-21. IIS Interface Timing (I2S Slave Mode Only) fSCL tSCLHIGH tSCLLOW IICSCL tSTOPH tBUF tSDAS tSTARTS IICSDA Figure 29-22.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA SD_CLK tHSDCD SD_CMD(out) tHSDCS tHSDCH SD_CMD(in) tHSDDD SD_DAT(out) tHSDDS tHSDDH SD_DAT(in) Figure 29-23. High Speed SDMMC Interface Timing SPICLK ` XspiMOSI (MO) ` ` tSPIMIH tSPIMOD XspiMISO (MI) ` ` ` ` tSPIMIS XspiMISO (SO) tSPISOD tSPISIH XspiMOSI (SI) ` ` ` ` tSPISIS tSPICSSD XspiCS tSPICSSS Figure 29-24.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR Rise Time Fall Time 90% VCRS 90% 10% 10% Differential Data Lines TR TF Figure 29-25. USB Timing (Data signal rise/fall time) Figure 29-26.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-8. Clock Timing Constants (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = -40 to 85°C, VDD_OP1 = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Unit Crystal clock input frequency fXTAL 10 - 30 MHz Crystal clock input cycle time tXTALCYC 33 - 100 ns External clock input frequency (note 1) fEXT 10 133 MHz External clock input cycle time (note 1) tEXTCYC 7.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR Table 29-9. SMC Timing Constants (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = -40 to 85°C, VDD_SRAM = 1.8V ± 0.1V) Parameter Symbol SMC Chip Select Delay tCSD Min Typ Max Unit bank0 2.3 - 5.72 ns bank1 2.2 6.40 bank2 2.1 6.28 bank3 2.5 7.59 bank4 2.3 6.28 bank5 2.2 6.40 SMC Output Enable Delay tOED 2.0 - 6.19 ns SMC Write Enable Delay tWED 2.1 - 6.06 ns SMC Address Delay tADDRD 2.3 - 6.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-11. Memory Interface Timing Constants (SDRAM) (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = -40 to 85°C, VDD_SDRAM = 1.8V ± 0.1V, 133MHz, CL = 15pF) Parameter Symbol Min Max Unit SDRAM Address Delay tSAD 1.65 4.25 ns SDRAM Chip Select Delay tSCSD 1.62 3.84 ns SDRAM Row active Delay tSRD 1.70 3.86 ns SDRAM Column active Delay tSCD 1.68 3.93 ns SDRAM Byte Enable Delay tSBED 1.63 4.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR Table 29-12. DMA Controller Module Signal Timing Constants (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = -40 to 85°C, VDD_OP2 = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Unit eXternal Request Setup tXRS 6.4/6.4 - 9.9/9.9 ns aCcess to Ack Delay when Low transition tCADL 3.1/2.8 7.8/7.1 ns aCcess to Ack Delay when High transition tCADH 2.8/2.5 7.8/6.9 ns tXAD 2 - HCLK eXternal Request Delay - Table 29-13.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-15. IIS Controller Module Signal Timing Constants(I2S Slave Mode Only) (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = –40 to 85 °C, VDD_OP2 = 3.3V ± 0.3V) Parameter Symbol Min. Typ. Max Unit LR Clock Input Delay TLRId 0 - ns Serial Data Setup Time TDS 10 - ns Serial Data Hold Time TDH 10 - ns Table 29-16. IIC BUS Controller Module Signal Timing (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR Table 29-17. High Speed SPI Interface Transmit/Receive Timing Constants (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = -40 to 85°C, VDD_SD = 3.3V ± 0.3V) (SPICLKout = 50Mhz, PAD loading = 30pF) Parameter Symbol Min Typ.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-18. USB Electrical Specifications (VDD12V = 1.2V ± 5%, TA = -40 to 85°C, VDDA33x = 3.3V ± 0.3V) Parameter Symbol Condition Min Max Unit - 100 mA Room Temp (25°C) - 500 µA Hot Temp (8°C) - 3 mA Supply Current Operating Current Suspended Current Input Levels for Full speed Differential Input Sensitivity VDI 0.2 Differential Common Mode Range VCM 0.8 2.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR Table 29-19. USB Full Speed Output Buffer Electrical Characteristics (VDDi = 1.3V± 0.05V (400MHz), VDDi = 1.2 V± 0.05V (533MHz), TA = -40 to 85°C, VDDA33x = 3.3V ± 0.3V) Parameter Symbol Condition Min Max Unit ns Driver Characteristics Transition Time Rise Time TR CL = 50pF 4.0 20 Fall Time TF CL = 50pF 4.0 20 Rise/Fall Time Matching TRFM (TR / TF ) 90 110 % Output Signal Crossover Voltage VCRS 1.3 2.
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S3C2450X RISC MICROPROCESSOR ELECTRICAL DATA Table 29-22. PCM Interface Timing (VDDiI = 1.0V± 0.05V, TA = -40 to 85°C, VDD = 3.3V ± 0.3V, 2.5V ± 0.2V, 1.8V ± 0.1V) Parameter Symbol Min. Typ. Max Unit 1/tCW 0.128 - 8.192 MHz PCMSCLK to PCMFSYNC delay tdFSYNC 0.5 - ns PCMSCLK to PCMSOUT delay tdSOUT 0.5 - ns PCMSIN setup time tsetupSIN 15 - ns PCMSIN hold time tholdSIN 10 - ns PCMSCLK clock width NOTE: This table is applied to PCM0 and PCM1, respectively.
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ELECTRICAL DATA S3C2450X RISC MICROPROCESSOR NOTES 29-32
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S3C2450X RISC MICROPROCESSOR 30 MECHANICAL DATA MECHANICAL DATA 1 PACKAGE DIMENSIONS Figure 30-1.
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MECHANICAL DATA S3C2450X RISC MICROPROCESSOR Figure 30-2.
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APPROVAL NO. ISSUE APPROVAL SHEET ITEM : PART NO.: APPROVAL NO. : APPROVAL MODEL : BLUETOOTH MODULE SBM2XA-05 1000AAA CONDITION : 1. 2. 3. 4. 상 SECTION Dept/Name DESIGNER CHECKED APPROVED DESIGNER H.T.SHIN CHECKED APPROVED Joseph,Lee customer SIGN SECTION Dept/Name SUPPLIER SIGN SUPPLIER : SungJin Techwin Co.,Ltd. ADDRESS : 256-8, In-Dong, Dong-Gu, Daejeon, Korea,300-828 042-271-1177(☎), 02-864-1091(R&D Center) Signature : 1.
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SBM2XA-05 Data Sheet APPROVAL SHEET CHANGE LIST DATE ISSUE 1.0 ITEM 2009.07.10 From ISSUE 1.0 To 1.1 2009.08.21 CONTENTS EVIDENCE 1st Draft Add certification Bluetooth SIG Qualification Design (QDL) Certificate RoHS From ISSUE To From ISSUE To From ISSUE To From ISSUE To From ISSUE To From ISSUE To From ISSUE To From ISSUE To From ISSUE To From ISSUE To Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet Contents 1. GENERAL PART..........................................................................................4 1.1 OVERVIEW.............................................................................................4 1.2 MAJOR FEATURES................................................................................4 1.3 MODULE BLOCK & INTERFACE............................................................4 1.4 MARKING AND EXTERNAL APPEARANCE..........................................
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SBM2XA-05 Data Sheet 1. General Part 1.1 Overview SBM2XA-05, This bluetooth handsfree module, provides a high quality, high integration, and cost effective solution for hands-free mobile communication such as Hands Free Car Kits or Telematics devices or luxury bluetooth Headset(mono,stereo) with noise&echo cancellation or portable bluetooth MP3 with RF tunning Further more,SungJin Techwin Co., Ltd.
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SBM2XA-05 Data Sheet 1.3 Module Block & Interface 1.4 Marking and External Appearance 1.4.1 Marking ① SBM ② ③ 10 00 ⓐ ⓑ 2 X A - 05 ④⑤⑥ ⑦ A A A ⓒ ⓓ ⓔ No Index No ① Manufacturer ⓐ ② ⓑ Manufactured Month ⓒ Manufactured Line ⓓ Manufactured Factory ⑤ Module’ s Abbreviation (SB : SUNGJIN Bluetooth) Application/Interface M : MM/ E : External Memory Class : (1 : Class 1) (2 : Class 2) Customer ⓔ History ⑥ PCB revision ⑦ CSR version (BC05) ③ ④ Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 1.4.2 External Appearance 1.4.3 Physical Dimension L1 SBM2XA-05 1000AAA Mark Dimension Mark Dimension Mark Dimension L 16.5±0.2 W 16.5±0.2 T 3±0.2 A 17.8±0.1 B 17.8±0.1 C 16.0±0.1 D 16.0±0.1 E 3.2±0.1 F 1.2±0.1 G 3.2±0.1 H 2.0±0.1 I 0.8±0.1 J 0.8±0.1 K 0.9±0.1 L1 0.8±0.1 M 2.0±0.1 Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 1.5 PIN Description Terminal No.
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SBM2XA-05 Data Sheet Analogue (28) IMIC BIAS (29) PIO[11] (30) PIO[10] (31) PIO[9] Bi-directional with programmable strength internal pull-up/down Programmable input/output line (32) PIO[8] Bi-directional with programmable strength internal pull-up/down Programmable input/output line (33) ANT (34) GND (35) PIO[3] (36) PIO[2] (37) PIO[1] (38) PIO[0] (39) (40) (41) (42) (43) Bi-directional with programmable strength internal pull-up/down Bi-directional with programmable strength in
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SBM2XA-05 Data Sheet 2. Specification 2.1 General Specification No Items Specification 1 Supply Voltage VCC : 2.7 ~ 3.7V 2 Carrier Frequency 2402MHz to 2480MHz (USA, Europe) 3 Modulation Method GFSK, π /4 DQPSK , 8DPSK 4 Transmission Power Max. 4dBm 5 Hopping 1600hpos/sec, 1MHz Channel space 6 Rx Sensitivity Typ. -87.5dBm 7 Output Interface UART, PIO,IIS,PCM 8 Compliant Bluetooth v2.1 + EDR 9 Built in Memory Flash memory(16Mbit) 10 Crystal 26MHz 2.
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SBM2XA-05 Data Sheet 2.3 TX/RX Specifications 2.3.1 TX Radio Characteristics Items Condition Min. Typ.
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SBM2XA-05 Data Sheet 2.3.2 RX Radio Characteristics Items Condition Sensitivity (single slot packets) Min. Typ. Max Unit Remark N&ETC -85 -78 dBm BER <0.1% Co-ch. NTC 9 11 dB 1MHz NTC -2 0 dB 2MHz NTC -34 -30 dB ≥ 3MHz NTC -43 -40 dB Image NTC -18 -9 dB Image± 1MHz NTC -23 -20 dB 30-2000M NTC 800M1000M NTC 10 dBm 1800M1900M NTC 10 dBm 20002399M NTC -27 dBm 24983000M NTC -27 dBm 3G12.
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SBM2XA-05 Data Sheet 2.4 Reliability Test Standard Test Item Conditions Step1 :150~170℃,70~175sec Reflow Test No.
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SBM2XA-05 Data Sheet 2.5 DAC Audio Interface Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 3. Application Note 3.1 Application Schematic Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 4. Recommanded Reflow Temperature ※ One Reflow Cycle is permissible Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 4.1 MS Level 3 Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 5. TEST REPORT SPEC No 1 2 3 4 ITEM MAKER OUTPUT VOLTAGE 1.8V±0.1 (at 0mA) SUPPLIER MAKER Maximum received signal at 0.1% BER BER < 0.100% RF transmit Power -6.00dBm < Pav < 4.00dBm SUPPLIER Initial carrier frequency tolerance ±75 KHz (max <= 75KHz) drift_rate <= 20.0KHz/50 us MAKER SUPPLIER MAKER SUPPLIER MAKER SUPPLIER f1 avg maximum Modulation 140.0KHz <= df1_avg <= 175.0KHz, f2avg/f1avgL df2/df1 >= 0.
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SBM2XA-05 Data Sheet 6 . T e st Proc e dure 6.1. OUTPUT VOLTAGE 1.8V±0.1 (at 0mA) 6.2. Maximum received signal at 0.1% BER(bit error rate) : BER < 0.100% 6.3. RF transmit Power : -6.00dBm < Pav < 4.00dBm 6.4. Modulation Characteristics : ±75 KHz (max <= 75KHz) : 6.5. Initial Carrier Frequency Tolerance (drift_rate) : <= 20.0KHz/50 us 6.6. CarrierFrequency Drift (f1 avg maximum Modulation) : 140.0KHz <= df1_avg <= 175.0KHz, 6.7. "CarrierFrequency Drift (f2avg/f1avgL) : df2/df1 >= 0.80% 6.8.
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SBM2XA-05 Data Sheet 7. PACKING INFORMATION 7.1 CARRIER SPECIFICATION 8.2 REEL SPECIFICATION Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 7.3 GIFT BOX SPECIFICATION 7.4 CARTON BOX SPECIFICATION Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 8. Bluetooth SIG Qualification Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 9. RoHS DATA 9.1 RoHS Copyright 2009 SungJin Techwin Co., Ltd..
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SBM2XA-05 Data Sheet 9.2 Crystal Resonator DSX321G Certificate of Conformity RoHS Copyright 2009 SungJin Techwin Co., Ltd..