Specifications

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DSI SS7HD Network Interface Boards Programmer's Manual Issue 11
91
Value
NETREF_2 clock mode
1
Drive NETREF_2 using clock recovered from highest priority line interface
6
Tristate (that is, not driven)
When the NETREF_2 signal is being driven, the clock source is the highest priority line
interface. If no interface is available for clock recovery, no signal is driven onto the
bus.
Driving the NETREF_2 signal is independent of the clk_mode and pll_clk_src settings
for this board.
clk_term
Determines whether the board is at either end of the CT Bus. Setting clock termination
prevents the bus clock signal being reflected and must be set for any board at either
end of the CT Bus (PCI only). The following table shows the permitted values and their
meanings.
Value
Clock Termination Mode
0
No change
1
Do not terminate the clock at this board
2
Terminate the clock at this board (PCI only)
Note: On CompactPCI boards, setting the clock termination has no effect.