Specifications

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DSI SS7HD Network Interface Boards Programmer's Manual Issue 11
89
Value
Bus speed
0
No change
3
8.192 MHz
clk_mode
Determines the clocking mode for the board. The following table shows the permitted
values and their meanings.
Value
Clock Mode
0
No change
1
CT Bus Primary Master, driving clock set A
2
CT Bus Secondary Master, driving clock set B
3
CT Bus Slave, initially using clock set A
4
CT Bus disabled
10
CT Bus Primary Master, driving clock set B
11
CT Bus Secondary Master, driving clock set A
12
CT Bus Slave, initially using clock set B
When mode 4 is selected (CT Bus disabled), the board is electrically isolated from the
other boards using the CT Bus. The CT Bus connection commands may still be used,
but the connections made are only be visible to this board. When using this mode, the
on-board clocks are synchronized to the configured pll_clk_src reference.
If the board is configured to be Slave to the CT Bus, it automatically switches between
using clock set A and clock set B if it detects a failure on the current clock set.
When a board is acting as Primary Master, it uses the clock reference set by the
pll_clk_src parameter to drive the CT Bus clock.
As Secondary Master, the pll_clk_src should be set to an appropriate source ready for
use if the board acting as Primary Master stops driving the CT Bus clock. Until this
time, the on-board clocks on the Secondary Master board are synchronized to the CT
Bus clock provided by the Primary Master.
pll_clk_src
Determines the source of the Phased Locked Loop (PLL) reference clock. The following
table shows the permitted values and their meanings.
Value
PLL clock source
0
No change
1
Clock recovered from one of the line interfaces according to priority order
5
Local reference oscillator