Specifications

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DSI SS7HD Network Interface Boards Programmer's Manual Issue 11
103
4.5.3 MVD_MSG_CLK_IND - Clock Event Indication
Synopsis
Message issued by the board to indicate on-board clocking related events.
Format
MESSAGE HEADER
Field Name
Meaning
type
MVD_MSG_CLK_IND (0x0e23)
id
0
src
MVD_TASK_ID
dst
MGMT_TASK_ID
rsp_req
0
hclass
0
status
event_id
err_info
0
len
0
The MVD_MSG_CLK_IND message header uses the following parameter:
event_id
Specifies the event that caused the indication to be generated. The following table
shows the possible values and their meanings.
Value
Description
1
Phased Locked Loop (PLL) entered holdover mode
Issued by boards acting as primary or secondary clock master when its nominated clock
reference becomes unavailable. The phase-locked-loop starts operating in holdover mode,
continuing to generate an on-board clock at the same frequency as the last valid reference
signal.
2
PLL left holdover mode
The nominated clock reference for a primary or secondary master board has become
available and is now being used as the input to the board’s clock circuitry.
3
CT Bus clock set A fail
The CT Bus clock set A signals are not being correctly driven.
4
CT Bus clock set A recover
The CT Bus clock set A signals are being driven.
5
CT Bus clock set B fail
The CT Bus clock set B signals are not being correctly driven,
6
CT Bus clock set B recover
The CT Bus clock set B signals are being driven.
7
Master clock changeover
The board issuing this indication has automatically changed from secondary master to
primary master role for the clock set it was configured to drive.