User's Manual

SC14SPNODE SF DECT Module with integrated Antenna and FLASH
© 2012 Dialog Semiconductor B.V. 10 Jul 1, 2014 v1.6
2.4 BLOCK DIAGRAM
2.5 POWER SUPPLY
Figure 3 shows the internal power supply circuit of the
SC14SPNODE SF.
2.6 ANTENNA OPERATION
Figure 4 shows the internal antenna circuit of the
SC14SPNODE SF. Pin RF0 is used for two external
antennas and can also be used for RF test purposes,
so it is recommended to add a 10 pF capacitor as
reserve pattern even when the two external antennas
are not used.
Re-certification of the SC14SPNODE SF is required if
at least one external antenna is added. On request,
Dialog Semiconductor can provide a pre-certified PCB
layout for an external antenna circuit.
RF1 is also recommended to use and can be con-
nected to the RF cable to be able to do the JPN DECT
type approval test.
2.6.1 Internal antenna only
The FAD function is not enabled if only the internal
antenna is used. In this case RFP0, RFP0n, P0 and
P0n must be left unconnected.
Figure 2 SC14SPNODE hardware block diagram
Charge Pump
doubler
32kByte
Shared
RAM
JTAG
/SDI
CR16Cplus
(82.944 MHz)
Non Shared/
Cache/Trace
RAM 16+4kByte
QSPI
ULE
Cache
Controller
DCDC
DIP
DIP RAM
LDO
Class-D
PCM / I2S
AFE
8/16 kHz
CODEC
8/16 kHz
48/2 kByte
Gen2DSP
ROM/RAM
Gen2DSP
82 MIPS
DMA
UART
GPIO 0-3
10 bit ADC
2 x ACCESS
APB bridge
SPI
UART
PLL
(165.888
MHz)
XTAL
20.736
MHz
Radio
Transceiver
PA
TX/RX
SW
ANT
SW
16Mbit
FLASH
Power supply
GPIOs
SC14SPNODE
Figure 3 Internal circuit of the power supply
UPL_MAIN_CTRL
VBATIN
100n
100n
1U0
VBATSW
VDDOUT
VDD
VBAT
TX BALUN
RF_SUPPLY
RF_SUPPLY_PA
CP_BAT
ULP_BAT
ADD
Internal
FLASH VDD
LDO_CTRL
Figure 4 Internal circuit of the antenna part
RF1
TP1
Internal antenna
RF0
P0n
P0
TX
RX
RFP0n
RFP0