User's Manual

UM-B-036
DA14580 Antenna module for QFN48 package
User manual
Revision 2.0
10
-
Dec
-
2014
CFR0012-00 Rev 1 11 of 34 © 2014
Dialog Semiconductor
Module GPIOs 4.7
The QFN48 antenna module provides 32 general purpose input/output pins (including JTAG signals).
The interfaces are multiplexed with the GPIOs and can be enabled by appropriate programming. The
available GPIO functions are presented in Table 3.
The following digital interfaces are available externally to the module:
● Two UARTs with hardware flow control up to 1 MBd
● SPI interface
● I
2
C bus at 100 kHz, 400 kHz
● 3-axis capable quadrature decoder
In addition, a 4-channel 10-bit ADC is also available externally to the module.
Table 3: GPIO pins: available functions
Interface Description Pins Comments
UART1 (UTX, URX) Bootable UART
P00, P01 57.6 kBd on booting
P02, P03 115.2 kBd on booting
P04,P05
57.6 kBd on booting.
This combination is selected for
the UART on this module.
P06, P07 9.6 kBd on booting
UART1 (RTS, CTS) Bootable UART
P02, P03
P06, P07
UART1 or UART2 UART debug port
Any port and any pin
combination
SPI
Bootable SPI P00, P03, P05, P06 Up to 8 MHz.
Non-bootable SPI
Any port and any pin
combination
I2C
Bootable I
2
C
P00, P01
100 kHz on booting for all
combinations
P02, P03
P04, P05
P06, P07
Non-bootable I
2
C Any port, any pin
ADC P00, P01, P02, P03
The voltage on these pins must be
lower than V
BAT
.
Test points Frequency calibration P05
16 MHz oscillator output. Can be
used for clock calibration.
Interrupts
Any port and any pin
combination
Keypad Any port , any pin column or row
Reset 4.7.1
The reset signal of the DA14580 (pin RST) is active high. On the QFN48 antenna module the RST
pin of the DA14580 is connected to GND via a resistor R8 (0 Ω). Consequently, the only way to
perform a hardware reset of the DA14580 on the antenna module is by switching off the power.