Datasheet

22
ENS160 Datasheet v0.95 preliminary / December 2020
14.2.3 SPI Read Operation
During a Read operation, data is clocked out on the falling edge of SCLK so it is stable for
the following riding edge.
MISO stays in high impedance mode until the device is selected (CSn low). Data on MISO is
only valid on a Read operation.
A transaction starts with the target address and R/W control bit in the first byte followed by
the read or write data.
In a Read operation Auto-increment of the address enables multiple registers to be read in
sequence. CSn de-asserting (to high) terminates the Read sequence.
A Read SPI frame is composed as follows:
Table 14: Read SPI Frame
Byte
Bit
Name
Description
0
7:1
AD[6:0]
On MOSI: Address of the register to Read
0
0
RW
On MOSI: 1: bytes are to be read, starting from AD[6:0].
1
7:0
RDATA[7:0]
Output on MISO; MOSI ignored
n
7:0
RDATA[7:0]
Output on MISO; MOSI ignored
14.2.4 SPI Write Operation
In a Write operation, the address does not Auto-increment. Multiple writes can be performed
by alternating Address and Data bytes. CSn de-asserting (to high) terminates the Write
sequence.
A Write SPI frame is composed as follows:
Table 15: Write SPI Frame
Byte
Bit
Name
Description
0
7:1
AD[6:0]
On MOSI: Address of the register to Write
0
0
RW
On MOSI: 0: bytes are to be Written, at AD[6:0].
1
7:0
WDATA[7:0]
Input on MOSI; MISO Dummy Data
even
7:1
AD[6:0]
On MOSI: Address of the register to Write
even
0
RW
On MOSI: 0: bytes are to be Written, at AD[6:0].
odd
7:0
WDATA[7:0]
Input on MOSI; MISO Dummy Data