Datasheet

ENS160 Datasheet v0.95 preliminary / December 2020
21
14.2 SPI Specification
14.2.1 SPI Description
The SPI interface is a slave bus operating up to 10MHz clock-frequency.
It shares pins with the I²C interface. SPI is selected and SPI transfer initiated by asserting
the CSn line low. Once the CSn line has been asserted low the ENS160 will not accept I²C
transactions until the next Power-On Reset.
Data is clocked in on the rising edge of SCLK; most significant bit first.
14.2.2 SPI Timing Information
Table 13: SPI Timings
Parameter
Symbol
Condition
Min
Typ
Max
Unit
SPI Clock (SCLK) Frequency
FSCLK
10
MHz
CSn falling to MISO Enabled
TEN
25pF load
20
ns
CSn rising to MISO Disable
TDIS
25pF load
20
ns
MOSI Setup Time before SCLK
TSUPI
15
ns
MOSI hold time after rising SCLK
THLDI
15
ns
CSn low to first rising SCLK
TLEAD
20
ns
Last SCLK low to CSn high
TLAG
20
ns
SCLK High Time
TSCLKH
40
ns
SCLK Low Time
TSCLKL
40
ns
SCLK falling to MISO Valid
TVALID
25pF load
40
ns
Figure 16 SPI Timings Reference
TSUPI
MOSI
ADDR6
ADDR5
TLEAD
TSCLKH
TSCLKL
TSCLK
TLAG
TSCSH
CSn
SCLK
THLDI
ADDR4-1
ADDR0
R/W
DATA_IN_MSB
DATA_IN
DATA_IN_LSB
TVALID
TDIS
THLDO
TRISE,TFALL
MISO
DATA_OUT_MSB
DATA_OUT_LSB
DATA_OUT
WRITE
SEQUENCE
READ
SEQUENCE
TEN